ATxmega256A3U Atmel Corporation, ATxmega256A3U Datasheet - Page 214

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ATxmega256A3U

Manufacturer Part Number
ATxmega256A3U
Description
Manufacturer
Atmel Corporation
Datasheets

Specifications of ATxmega256A3U

Flash (kbytes)
256 Kbytes
Pin Count
64
Max. Operating Frequency
32 MHz
Cpu
8-bit AVR
# Of Touch Channels
16
Hardware Qtouch Acquisition
No
Max I/o Pins
50
Ext Interrupts
50
Usb Transceiver
1
Usb Speed
Full Speed
Usb Interface
Device
Spi
10
Twi (i2c)
2
Uart
7
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
16
Adc Resolution (bits)
12
Adc Speed (ksps)
2000
Analog Comparators
4
Resistive Touch Screen
No
Dac Channels
2
Dac Resolution (bits)
12
Temp. Sensor
Yes
Crypto Engine
AES/DES
Sram (kbytes)
16
Eeprom (bytes)
4096
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
Yes
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.6 to 3.6
Operating Voltage (vcc)
1.6 to 3.6
Fpu
No
Mpu / Mmu
no / no
Timers
7
Output Compare Channels
22
Input Capture Channels
22
Pwm Channels
22
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes

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17.3
17.3.1
17.4
8331A–AVR–07/11
Address
+0x00
Register Description
Register Summary
CTRLA – Hi-Res Control Register A
Name
CTRLA
The hi-res extension will not output any pulse shorter than one peripheral clock cycle; i.e., a
compare value lower than four will have no visible output.
• Bit 7:3 – Reserved
These bits are reserved and will always be read as zero. For compatibility with future devices,
always write these bits to zero when this register is written.
• Bit 2 – HRPLUS: High Resolution Plus
Setting this bit enables high resolution plus. Hi-res plus is the same as hi-res, but will increase
the resolution by eight (3 bits) instead of four.
The extra resolution is achieved by operating at both edges of the peripheral 4x clock.
• Bit 1:0 – HREN[1:0]: High Resolution Enable
These bits enables the high-resolution mode for a timer/counter according to
Setting one or both HREN bits will enable high-resolution waveform generation output for the
entire general purpose I/O port. This means that both timer/counters connected to the same port
must enable hi-res if both are used for generating PWM or FRQ output on pins.
Table 17-1.
Bit
+0x00
Read/Write
Initial Value
Bit 7
HREN[1:0]
High Resolution Enable
00
01
10
11
Bit 6
R
7
0
R
6
0
Bit 5
High Resolution Enabled
None
Timer/counter 0
Timer/counter 1
Both timer/counters
R
5
0
Bit 4
R
4
0
Bit 3
Atmel AVR XMEGA AU
R
3
0
HRPLUS
Bit 2
HRPLUS
R/W
2
0
Bit 1
R/W
1
0
HREN[1:0]
HREN[1:0]
Table
R/W
Bit 0
0
0
17-1.
CTRLA
Page
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