ATxmega256A3U Atmel Corporation, ATxmega256A3U Datasheet - Page 112

• Manufacturer Part Number: ATxmega256A3U
• Manufacturer: Atmel Corporation

Specifications of ATxmega256A3U

• Flash (kbytes): 256 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 32 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 50
• Ext Interrupts: 50
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 10
• Twi (i2c): 2
• Uart: 7
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 16
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 4
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 12
• Temp. Sensor: Yes
• Crypto Engine: AES/DES
• Sram (kbytes): 16
• Eeprom (bytes): 4096
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.6 to 3.6
• Operating Voltage (vcc): 1.6 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 7
• Output Compare Channels: 22
• Input Capture Channels: 22
• Pwm Channels: 22
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

9.3
9.3.1
8331A–AVR–07/11
Reset Sequence
Reset Counter
Figure 9-1.
A reset request from any reset source will immediately reset the device and keep it in reset as
long as the request is active. When all reset requests are released, the device will go through
three stages before the device starts running again:
If another reset requests occurs during this process, the reset sequence will start over again.
The reset counter can delay reset release with a programmable period from when all reset
requests are released. The reset delay is timed from the 1kHz output of the ultra low power
(ULP) internal oscillator, and in addition 24 System clock
is released. The reset delay is set by the STARTUPTIME fuse bits. The selectable delays are
shown in
Table 9-1.
SUT[1:0]
• Reset counter delay
• Oscillator startup
• Oscillator calibration
00
01
10
11
Table
Number of 1kHz ULP Oscillator Clock Cycles
64K Clk
Reserved
24 Clk
4K Clk
BODLEVEL [2:0]
Pull-up Resistor
Reset system overview.
Reset delay.
9-1.
SYS
ULP
FILTER
SPIKE
ULP
+ 24 Clk
+ 24 Clk
SYS
SYS
Power-on Reset
SUT[1:0]
Brown-out
Watchdog
Oscillator
External
Software
Reset
Reset
Reset
Reset
Reset
ULP
PDI
Register (MCUSR)
MCU Status
Atmel AVR XMEGA AU
(clk
Stable frequency at startup
Slowly rising power
-
Fast rising power or BOD enabled
Delay Counters
SYS
) cycles are counted before reset
Recommended Usage
TIMEOUT
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