ATxmega256A3U Atmel Corporation, ATxmega256A3U Datasheet - Page 205

• Manufacturer Part Number: ATxmega256A3U
• Manufacturer: Atmel Corporation

Specifications of ATxmega256A3U

• Flash (kbytes): 256 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 32 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 50
• Ext Interrupts: 50
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 10
• Twi (i2c): 2
• Uart: 7
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 16
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 4
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 12
• Temp. Sensor: Yes
• Crypto Engine: AES/DES
• Sram (kbytes): 16
• Eeprom (bytes): 4096
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.6 to 3.6
• Operating Voltage (vcc): 1.6 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 7
• Output Compare Channels: 22
• Input Capture Channels: 22
• Pwm Channels: 22
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

16.5
8331A–AVR–07/11
Pattern Generation
The DTI unit consists of four equal dead-time generators, one for each compare channel in
timer/counter 0.
four channels have a common register that controls the dead time. The high side and low side
have independent dead-time setting, and the dead-time registers are double buffered.
Figure 16-3. Dead-time generator block diagram.
As shown in
each peripheral clock cycle, until it reaches zero. A nonzero counter value will force both the low
side and high side outputs into their OFF state. When a change is detected on the WG output,
the dead-time counter is reloaded according to the edge of the input. A positive edge initiates a
counter reload of the DTLS register, and a negative edge a reload of DTHS register.
Figure 16-4. Dead-time generator timing diagram.
The pattern generator unit reuses the DTI registers to produce a synchronized bit pattern across
the port it is connected to. In addition, the waveform generator output from compare channel A
(CCA) can be distributed to and override all the port pins. These features are primarily intended
for handling the commutation sequence in brushless DC motor (BLDC) and stepper motor appli-
WG output
"WG output"
"DTLS"
"DTHS"
"dti_cnt"
Figure 16-4 on page
Dead Time Generator
Figure 16-3 on page 205
D
Q
t
DTILS
Edge Detect
BV
t
205, the 8-bit dead-time counter is decremented by one for
P
DTLSBUF
DTILS
shows the block diagram of one DTI generator. The
t
Atmel AVR XMEGA AU
T
DTIHS
BV
LOAD
E
Counter
DTHSBUF
= 0
DTIHS
"DTLS"
(To PORT)
"DTHS"
(To PORT)
205