ATxmega256A3U Atmel Corporation, ATxmega256A3U Datasheet - Page 386

• Manufacturer Part Number: ATxmega256A3U
• Manufacturer: Atmel Corporation

Specifications of ATxmega256A3U

• Flash (kbytes): 256 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 32 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 50
• Ext Interrupts: 50
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 10
• Twi (i2c): 2
• Uart: 7
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 16
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 4
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 12
• Temp. Sensor: Yes
• Crypto Engine: AES/DES
• Sram (kbytes): 16
• Eeprom (bytes): 4096
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.6 to 3.6
• Operating Voltage (vcc): 1.6 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 7
• Output Compare Channels: 22
• Input Capture Channels: 22
• Pwm Channels: 22
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

29.10.3
8331A–AVR–07/11
CTRLC – Control Register C
Table 29-1.
• Bit 4:2 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always
write these bits to zero when this register is written.
• Bit 1 – CH1TRIG: DAC Auto trigged mode Channel 1
If this bit is set, an event on the configured event channel, set in EVCTRL, will trigger conversion
on DAC channel 1 if its data register, CH1DATA, has been updated.
• Bit 0 – CH0TRIG: DAC Auto trigged mode Channel 0
If this bit is set, an event on the configured event channel, set in EVCTRL, will trigger conversion
on DAC channel 1 if its data register, CH0DATA, has been updated.
• Bit 7:5 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always
write these bits to zero when this register is written.
• Bit 4:3 – REFSEL[1:0]: DAC Reference Selection
These bits select the reference for the DAC according to
Table 29-2.
• Bit 2:1 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always
write these bits to zero when this register is written.
Bit
+0x02
Read/Write
Initial Value
CHSEL[1:0]
REFSEL[1:0]
00
01
10
11
00
01
10
11
R
7
–
0
DAC channel selection
DAC Reference selection
Group Configuration
SINGLE
SINGLE1
DUAL
-
R
6
–
0
Group Configuration
INT1V
AVCC
AREFA
AREFB
R
5
–
0
R/W
4
0
REFSEL[1:0]
Single channel operation on channel 0
Single channel operation on channel 1
Description
Dual channel operation
Reserved
R/W
Atmel AVR XMEGA AU
3
0
Table 29-2 on page
R/W
2
–
0
AREF on PORTB
AREF on PORTA
Internal 1.00 V
Description
AV
R/W
1
–
0
CC
386.
LEFTADJ
R/W
0
0
CTRLC
386