ATxmega256A3U Atmel Corporation, ATxmega256A3U Datasheet - Page 115

• Manufacturer Part Number: ATxmega256A3U
• Manufacturer: Atmel Corporation

Specifications of ATxmega256A3U

• Flash (kbytes): 256 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 32 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 50
• Ext Interrupts: 50
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 10
• Twi (i2c): 2
• Uart: 7
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 16
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 4
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 12
• Temp. Sensor: Yes
• Crypto Engine: AES/DES
• Sram (kbytes): 16
• Eeprom (bytes): 4096
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.6 to 3.6
• Operating Voltage (vcc): 1.6 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 7
• Output Compare Channels: 22
• Input Capture Channels: 22
• Pwm Channels: 22
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

9.4.3
9.4.4
8331A–AVR–07/11
External Reset
Watchdog Reset
The BODACT fuse determines the BOD setting for active mode and idle mode, while the
BODPD fuse determines the brownout detection setting for all sleep modes, except idle mode.
Table 9-3.
The external reset circuit is connected to the external RESET pin. The external reset will trigger
when the RESET pin is driven below the RESET pin threshold voltage, V
minimum pulse period, t
includes an internal pull-up resistor.
Figure 9-5.
For external reset characterization data consult the device datasheet.
The watchdog timer (WDT) is a system function for monitoring correct program operation. If the
WDT is not reset from the software within a programmable timout period, a watchdog reset will
be given. The watchdog reset is active for one to two clock cycles of the 2MHz internal oscillator.
• Enabled: In this mode, the V
• Sampled: In this mode, the BOD circuit will sample the V
for a period of t
that of the 1kHz output from the ultra low power (ULP) internal oscillator. Between each
sample, the BOD is turned off. This mode will reduce the power consumption compared to
the enabled mode, but a fall in the V
oscillator output will not be detected. If a brownout is detected in this mode, the BOD circuit is
set in enabled mode to ensure that the device is kept in reset until V
CC
BOD setting fuse decoding.
External reset characteristics.
BOD
BODACT[1:0]/ BODPD[1:0]
will give a brownout reset
EXT
t
EXT
. The reset will be held as long as the pin is kept low. The RESET pin
CC
00
01
10
11
level is continuously monitored, and a drop in V
CC
level between two positive edges of the 1kHz ULP
Atmel AVR XMEGA AU
CC
level with a period identical to
CC
RST
is above V
, for longer than the
Reserved
Sampled
Disabled
Enabled
Mode
CC
below V
BOT
again
115
BOT