M55800A Atmel Corporation, M55800A Datasheet - Page 136
M55800A
Manufacturer Part Number
M55800A
Description
Manufacturer
Atmel Corporation
Datasheets
1.M40800.pdf
(284 pages)
2.M40800.pdf
(153 pages)
3.M55800A.pdf
(29 pages)
4.M55800A.pdf
(256 pages)
5.M55800A.pdf
(28 pages)
Specifications of M55800A
Flash (kbytes)
0 Kbytes
Pin Count
176
Max. Operating Frequency
33 MHz
Cpu
ARM7TDMI
Hardware Qtouch Acquisition
No
Max I/o Pins
58
Ext Interrupts
58
Usb Speed
No
Usb Interface
No
Spi
1
Uart
3
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
72
Resistive Touch Screen
No
Dac Channels
1
Dac Resolution (bits)
10
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
8
Self Program Memory
NO
External Bus Interface
1
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
3.3/5.0
Fpu
No
Mpu / Mmu
no / no
Timers
6
Output Compare Channels
6
Input Capture Channels
6
32khz Rtc
Yes
Calibrated Rc Oscillator
No
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18.2
Figure 18-2. Baud Rate Generator
136
MCK/8
MCK
SCK
Baud Rate Generator
AT91M5880A
USCLKS [0]
0
1
USCLKS [1]
The Baud Rate Generator provides the bit period clock (the Baud Rate clock) to both the
Receiver and the Transmitter.
The Baud Rate Generator can select between external and internal clock sources. The external
clock source is SCK. The internal clock sources can be either the master clock MCK or the mas-
ter clock divided by 8 (MCK/8).
Note:
When the USART is programmed to operate in Asynchronous Mode (SYNC = 0 in the Mode
Register US_MR), the selected clock is divided by 16 times the value (CD) written in US_BRGR
(Baud Rate Generator Register). If US_BRGR is set to 0, the Baud Rate Clock is disabled.
When the USART is programmed to operate in Synchronous Mode (SYNC = 1) and the selected
clock is internal (USCLKS[1] = 0 in the Mode Register US_MR), the Baud Rate Clock is the
internal selected clock divided by the value written in US_BRGR. If US_BRGR is set to 0, the
Baud Rate Clock is disabled.
In Synchronous Mode with external clock selected (USCLKS[1] = 1), the clock is provided
directly by the signal on the SCK pin. No division is active. The value written in US_BRGR has
no effect.
0
1
Baud Rate
Baud Rate
In all cases, if an external clock is used, the duration of each of its levels must be longer than the
system clock (MCK) period. The external clock frequency must be at least 2.5 times lower than the
system clock.
CLK
=
=
16-bit Counter
CD
Selected Clock
Selected Clock
16 x CD
CD
USCLKS [1]
SYNC
OUT
0
CD
>1
1
0
0
1
Divide
by 16
SYNC
0
1
1745F–ATARM–06-Sep-07
Baud Rate
Clock
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