M55800A Atmel Corporation, M55800A Datasheet - Page 61
M55800A
Manufacturer Part Number
M55800A
Description
Manufacturer
Atmel Corporation
Datasheets
1.M40800.pdf
(284 pages)
2.M40800.pdf
(153 pages)
3.M55800A.pdf
(29 pages)
4.M55800A.pdf
(256 pages)
5.M55800A.pdf
(28 pages)
Specifications of M55800A
Flash (kbytes)
0 Kbytes
Pin Count
176
Max. Operating Frequency
33 MHz
Cpu
ARM7TDMI
Hardware Qtouch Acquisition
No
Max I/o Pins
58
Ext Interrupts
58
Usb Speed
No
Usb Interface
No
Spi
1
Uart
3
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
72
Resistive Touch Screen
No
Dac Channels
1
Dac Resolution (bits)
10
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
8
Self Program Memory
NO
External Bus Interface
1
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
3.3/5.0
Fpu
No
Mpu / Mmu
no / no
Timers
6
Output Compare Channels
6
Input Capture Channels
6
32khz Rtc
Yes
Calibrated Rc Oscillator
No
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12.8
1745F–ATARM–06-Sep-07
First Start-up Sequence
At initial startup, or after VDDBU has been disconnected, the battery-supplied logic must be
initialized.
The Battery Backup Reset sets the following default state:
A simple RC network can be used as a power-on reset for the battery supply.
The pin SHDN is tri-stated by default. An external resistor must hold the main power supply
shut-down pin in the inactive state. The shut-down logic can be programmed with the correct
active level of the power supply shut-down input during the first start-up sequence.
The first time the system is powered up, the SHDN pin is tri-stated because different power sup-
plies use different logic levels for their shut-down input signals. To minimize backup battery
power consumption, there is no internal pull-up or pull-down on this signal.
If the power supply needs a logic level on its shut-down input in order to start the main power
supply then an external “Force Start Up” jumper is required to provide this level.
The jumper provides the necessary level on the SHDN to maintain the power supply when the
AT91 boots, and it can be removed until the next loss of battery power.
• Shut-down Logic
• The Power Mode Register
• The Real-time Clock Configuration and Data Registers
Initialized in the Wake-up state (or Non Alarm)
Shut-down defines SHDN as level 0 (SHDALS = 1)
Wake-up defines SHDN as tri-state (WKACKS = 0)
AT91M5880A
61
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