M55800A Atmel Corporation, M55800A Datasheet - Page 191

• Manufacturer Part Number: M55800A
• Manufacturer: Atmel Corporation

Specifications of M55800A

• Flash (kbytes): 0 Kbytes
• Pin Count: 176
• Max. Operating Frequency: 33 MHz
• Cpu: ARM7TDMI
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 58
• Ext Interrupts: 58
• Usb Speed: No
• Usb Interface: No
• Spi: 1
• Uart: 3
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 72
• Resistive Touch Screen: No
• Dac Channels: 1
• Dac Resolution (bits): 10
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 8
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.3/5.0
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

Table 20-1.
Notes:
20.2
20.2.1
1745F–ATARM–06-Sep-07
Pin Name
Master In Slave Out
Master Out Slave In
Serial Clock
Peripheral Chip Selects
Peripheral Chip Select/
Slave Select
1. After a hardware reset, the SPI clock is disabled by default. The user must configure the Power Management Controller
2. After a hardware reset, the SPI pins are deselected by default (see
Master Mode
Fixed Peripheral Select
before any access to the User Interface of the SPI.
The user must configure the PIO Controller to enable the corresponding pins for their SPI function. NPCS0/NSS must be
configured as open drain in the Parallel I/O Controller for multi-master operation.
SPI Pins
In Master Mode, the SPI controls data transfers to and from the slave(s) connected to the SPI
bus. The SPI drives the chip select(s) to the slave(s) and the serial clock (SPCK). After enabling
the SPI, a data transfer begins when the ARM core writes to the SP_TDR (Transmit Data
Register).
Transmit and Receive buffers maintain the data flow at a constant rate with a reduced require-
ment for high priority interrupt servicing. When new data is available in the SP_TDR (Transmit
Data Register) the SPI continues to transfer data. If the SP_RDR (Receive Data Register) has
not been read before new data is received, the Overrun Error (OVRES) flag is set.
The delay between the activation of the chip select and the start of the data transfer (DLYBS) as
well as the delay between each data transfer (DLYBCT) can be programmed for each of the four
external chip selects. All data transfer characteristics including the two timing values are pro-
grammed in registers SP_CSR0 to SP_CSR3 (Chip Select Registers). See
In master mode the peripheral selection can be defined in two different ways:
Figures 20-2 and 20-3 show the operation of the SPI in Master Mode. For details concerning the
flag and control bits in these diagrams, see the tables in the Programmer’s Model, starting on
page 198.
This mode is ideal for transferring memory blocks without the extra overhead in the transmit data
register to determine the peripheral.
Fixed Peripheral Select is activated by setting bit PS to zero in SP_MR (Mode Register). The
peripheral is defined by the PCS field, also in SP_MR.
This option is only available when the SPI is programmed in master mode.
• Fixed Peripheral Select: SPI exchanges data with only one peripheral
• Variable Peripheral Select: Data can be exchanged with more than one peripheral
Mnemonic
NPCS[3:1]
NPCS0/
SPCK
MISO
MOSI
NSS
Master
Master
Master
Master
Master
Master
Mode
Slave
Slave
Slave
Slave
Function
Serial data input to SPI
Serial data output from SPI
Serial data output from SPI
Serial data input to SPI
Clock output from SPI
Clock input to SPI
Select peripherals
Output: Selects peripheral
Input: low causes mode fault
Input: chip select for SPI
Section 16. “PIO: Parallel I/O Controller” on page
AT91M5880A
Table
20-2.
113).
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