M55800A Atmel Corporation, M55800A Datasheet - Page 67
M55800A
Manufacturer Part Number
M55800A
Description
Manufacturer
Atmel Corporation
Datasheets
1.M40800.pdf
(284 pages)
2.M40800.pdf
(153 pages)
3.M55800A.pdf
(29 pages)
4.M55800A.pdf
(256 pages)
5.M55800A.pdf
(28 pages)
Specifications of M55800A
Flash (kbytes)
0 Kbytes
Pin Count
176
Max. Operating Frequency
33 MHz
Cpu
ARM7TDMI
Hardware Qtouch Acquisition
No
Max I/o Pins
58
Ext Interrupts
58
Usb Speed
No
Usb Interface
No
Spi
1
Uart
3
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
72
Resistive Touch Screen
No
Dac Channels
1
Dac Resolution (bits)
10
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
8
Self Program Memory
NO
External Bus Interface
1
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
3.3/5.0
Fpu
No
Mpu / Mmu
no / no
Timers
6
Output Compare Channels
6
Input Capture Channels
6
32khz Rtc
Yes
Calibrated Rc Oscillator
No
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- M55800A PDF datasheet #3
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• MUL: Phase Lock Loop Factor
0 = The PLL is deactivated, reducing power consumption to a minimum.
1 - 63 = The PLL output is at a higher frequency (MUL+1) than the input if the bit lock is set in APMC_SR.
• CSS: Clock Source Selection
• OSCOUNT: Main Oscillator Counter
Specifies the number of 32,768 Hz divided by 8 clock cycles for the main oscillator start-up timer to count before the main
oscillator is stabilized, after the oscillator is enabled. The main oscillator counter is a down-counter which is preloaded with
the OSCOUNT value when the MOSCEN bit in the Clock Generator Mode register (CGMR) is set, but only if the
OSCOUNT value is different from 0x0.
• PLLCOUNT: PLL Lock Counter
Specifies the number of 32,768 Hz clock cycles for the PLL lock timer to count before the PLL is locked, after the PLL is
started. The PLL counter is a down-counter which is preloaded with the PLLCOUNT value when the MUL field in the Clock
Generator Mode register (CGMR) is modified, but only if the MUL value is different from 0 (PLL disabled) and also the
PLLCOUNT value itself different from 0x0. PLLCOUNT must be loaded with a minimum value of 2 in order to guarantee a
time of at least one slow clock period.
1745F–ATARM–06-Sep-07
0
0
1
1
CSS
0
1
0
1
Clock Source Selection
Low-frequency clock provided by the RTC
Main oscillator Output or external clock
Phase Lock Loop Output
Reserved
Code Label
APMC_CSS_LF
APMC_CSS_MOSC
APMC_CSS_PLL
–
AT91M5880A
67
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