M55800A Atmel Corporation, M55800A Datasheet - Page 197
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M55800A
Manufacturer Part Number
M55800A
Description
Manufacturer
Atmel Corporation
Datasheets
1.M40800.pdf
(284 pages)
2.M40800.pdf
(153 pages)
3.M55800A.pdf
(29 pages)
4.M55800A.pdf
(256 pages)
5.M55800A.pdf
(28 pages)
Specifications of M55800A
Flash (kbytes)
0 Kbytes
Pin Count
176
Max. Operating Frequency
33 MHz
Cpu
ARM7TDMI
Hardware Qtouch Acquisition
No
Max I/o Pins
58
Ext Interrupts
58
Usb Speed
No
Usb Interface
No
Spi
1
Uart
3
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
72
Resistive Touch Screen
No
Dac Channels
1
Dac Resolution (bits)
10
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
8
Self Program Memory
NO
External Bus Interface
1
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
3.3/5.0
Fpu
No
Mpu / Mmu
no / no
Timers
6
Output Compare Channels
6
Input Capture Channels
6
32khz Rtc
Yes
Calibrated Rc Oscillator
No
- M40800 PDF datasheet
- M40800 PDF datasheet #2
- M55800A PDF datasheet #3
- M55800A PDF datasheet #4
- M55800A PDF datasheet #5
- Current page: 197 of 256
- Download datasheet (5Mb)
Figure 20-6. Programmable Delays (DLYBCS, DLYBS and DLYBCT)
20.5
20.6
1745F–ATARM–06-Sep-07
SPCK Output
Chip Select 2
Chip Select 1
Clock Generation
Peripheral Data Controller
In master mode the SPI Master Clock is either MCK or MCK/32, as defined by the MCK32 field
of SP_MR. The SPI baud rate clock is generated by dividing the SPI Master Clock by a value
between 4 and 510. The divisor is defined in the SCBR field in each Chip Select Register. The
transfer speed can thus be defined independently for each chip select signal.
CPOL and NCPHA in the Chip Select Registers define the clock/data relationship between mas-
ter and slave devices. CPOL defines the inactive value of the SPCK. NCPHA defines which
edge causes data to change and which edge causes data to be captured.
In Slave Mode, the input clock low and high pulse duration must strictly be longer than two sys-
tem clock (MCK) periods.
The SPI is closely connected to two Peripheral Data Controller channels. One is dedicated to
the receiver. The other is dedicated to the transmitter.
The PDC channel is programmed using SP_TPR (Transmit Pointer) and SP_TCR (Transmit
Counter) for the transmitter and SP_RPR (Receive Pointer) and SP_RCR (Receive Counter) for
the receiver. The status of the PDC is given in SP_SR by the SPENDTX bit for the transmitter
and by the SPENDRX bit for the receiver.
The pointer registers (SP_TPR and SP_RPR) are used to store the address of the transmit or
receive buffers. The counter registers (SP_TCR and SP_RCR) are used to store the size of
these buffers.
The receiver data transfer is triggered by the RDRF bit and the transmitter data transfer is trig-
gered by TDRE. When a transfer is performed, the counter is decremented and the pointer is
incremented. When the counter reaches 0, the status bit is set (SPENDRX for the receiver,
SPENDTX for the transmitter in SP_SR) and can be programmed to generate an interrupt. While
the counter is at zero, the status bit is asserted and transfers are disabled.
Change peripheral
DLYBCS
DLYBS
of peripheral
No change
DLYBCT
AT91M5880A
DLYBCT
197
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