SAM3SD8C Atmel Corporation, SAM3SD8C Datasheet - Page 1057

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SAM3SD8C

Manufacturer Part Number
SAM3SD8C
Description
Manufacturer
Atmel Corporation
Datasheets
39.7.4
Name:
Address:
Access:
This register can only be written if the WPEN bit is cleared in
• CHx: Channel x Disable
0 = No effect.
1 = Disables the corresponding channel.
Warning: If the corresponding channel is disabled during a conversion or if it is disabled then re-enabled during a conver-
sion, its associated analog value and its corresponding EOC flags in DACC_ISR are unpredictable.
11090A–ATARM–10-Feb-12
11090A–ATARM–10-Feb-12
31
23
15
7
DACC Channel Disable Register
30
22
14
DACC_CHDR
0x4003C014
Write-only
6
29
21
13
5
28
20
12
4
DACC Write Protect Mode
27
19
11
3
26
18
10
2
Register.
SAM3S8/SD8
SAM3S8/SD8
CH1
25
17
9
1
CH0
24
16
8
0
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