SAM3SD8C Atmel Corporation, SAM3SD8C Datasheet - Page 886

• Manufacturer Part Number: SAM3SD8C
• Manufacturer: Atmel Corporation

886
886
SAM3S8/SD8
SAM3S8/SD8
When the fault protection is triggered on a channel, the fault protection mechanism forces the
channel outputs to the values defined by the fields FPVHx and FPVLx in the
tion Value Register”
forcing is made asynchronously to the channel counter.
CAUTION:
If a comparison unit is enabled (see
triggered in the channel 0, in this case the comparison cannot match.
As soon as the fault protection is triggered on a channel, an interrupt (different from the interrupt
generated at the end of the PWM period) can be generated but only if it is enabled and not
masked. The interrupt is reset by reading the interrupt status register, even if the fault which has
caused the trigger of the fault protection is kept active.
• To prevent an unexpected activation of the status flag FSy in the PWM_FSR register, the
• To prevent an unexpected activation of the Fault Protection on the channel x, the bit FPEx[y]
FMODy bit can be set to “1” only if the FPOLy bit has been previously configured to its final
value.
can be set to “1” only if the FPOLy bit has been previously configured to its final value.
(PWM_FPV) and leads to a reset of the counter of this channel. The output
Section 35.6.3 “PWM Comparison
Units”) and if a fault is
11090A–ATARM–10-Feb-12
11090A–ATARM–10-Feb-12
“PWM Fault Protec-