SAM3SD8C Atmel Corporation, SAM3SD8C Datasheet - Page 446

• Manufacturer Part Number: SAM3SD8C
• Manufacturer: Atmel Corporation

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446
SAM3S8/SD8
SAM3S8/SD8
Whenever the PLL is re-enabled or one of its parameters is changed, the LOCK (LOCKA,
LOCKB) bit in PMC_SR is automatically cleared. The values written in the PLLCOUNT field
(PLLACOUNT, PLLBCOUNT) in CKGR_PLLR (CKGR_PLLAR, CKGR_PLLBR) are loaded in
the PLL counter. The PLL counter then decrements at the speed of the Slow Clock until it
reaches 0. At this time, the LOCK bit is set in PMC_SR and can trigger an interrupt to the pro-
cessor. The user has to load the number of Slow Clock cycles required to cover the PLL
transient time into the PLLCOUNT field.
The PLL clock can be divided by 2 by writing the PLLDIV2 (PLLADIV2, PLLBDIV2) bit in PMC
Master Clock Register (PMC_MCKR).
It is forbidden to change 4/8/12 MHz Fast RC oscillator, or main selection in CKGR_MOR regis-
ter while Master clock source is PLL and PLL reference clock is the Fast RC oscillator.
The user must:
• Switch on the Main RC oscillator by writing 1 in CSS field of PMC_MCKR.
• Change the frequency (MOSCRCF) or oscillator selection (MOSCSEL) in CKGR_MOR.
• Wait for MOSCRCS (if frequency changes) or MOSCSELS (if oscillator selection changes) in
• Disable and then enable the PLL (LOCK in PMC_IDR and PMC_IER).
• Wait for PLLRDY.
• Switch back to PLL.
PMC_IER.
11090A–ATARM–10-Feb-12
11090A–ATARM–10-Feb-12