SAM3SD8C Atmel Corporation, SAM3SD8C Datasheet - Page 473

• Manufacturer Part Number: SAM3SD8C
• Manufacturer: Atmel Corporation

25.1.16.10
Name:
Address:
Access:
Possible limitations on PLLB input frequencies and multiplier factors should be checked before using the PMC.
This register can only be written if the WPEN bit is cleared in
• DIVB: Divider
• PLLBCOUNT: PLLB Counter
Specifies the number of Slow Clock cycles x8 before the LOCKB bit is set in PMC_SR after CKGR_PLLBR is written.
• MULB: PLLB Multiplier
0 = The PLLB is deactivated.
1 up to 36 = The PLLB Clock frequency is the PLLB input frequency multiplied by MULB + 1.
11090A–ATARM–10-Feb-12
11090A–ATARM–10-Feb-12
DIVB
0
1
2 - 255
31
23
15
–
–
7
PMC Clock Generator PLLB Register
CKGR_PLLBR
0x400E042C
Read-write
30
22
14
–
–
6
Divider Selected
Divider output is 0
Divider is bypassed (DIVB=1)
Divider output is DIVB
29
21
13
–
5
28
20
12
–
4
MULB
DIVB
“PMC Write Protect Mode Register”
27
19
11
–
3
PLLBCOUNT
26
18
10
2
MULB
SAM3S8/SD8
SAM3S8/SD8
.
25
17
9
1
24
16
8
0
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