SAM3SD8C Atmel Corporation, SAM3SD8C Datasheet - Page 715

• Manufacturer Part Number: SAM3SD8C
• Manufacturer: Atmel Corporation

11090A–ATARM–10-Feb-12
11090A–ATARM–10-Feb-12
Drift Compensation
Figure 32-10. Start Frame Delimiter
Drift compensation is available only in 16X oversampling mode. An hardware recovery system
allows a larger clock drift. To enable the hardware system, the bit in the USART_MAN register
must be set. If the RXD edge is one 16X clock cycle from the expected edge, this is considered
as normal jitter and no corrective actions is taken. If the RXD event is between 4 and 2 clock
cycles before the expected edge, then the current period is shortened by one clock cycle. If the
RXD event is between 2 and 3 clock cycles after the expected edge, then the current period is
lengthened by one clock cycle. These intervals are considered to be drift and so corrective
actions are automatically taken.
Figure 32-11. Bit Resynchronization
Oversampling
Sampling
16x Clock
point
RXD
Manchester
Manchester
Manchester
encoded
encoded
encoded
data
data
data
Preamble Length
Txd
Txd
Txd
Synchro.
Error
is set to 0
Synchro.
SFD
SFD
SFD
Jump
DATA
One bit start frame delimiter
Expected edge
Tolerance
start frame delimiter
start frame delimiter
DATA
DATA
Command Sync
Jump
Sync
Data Sync
SAM3S8/SD8
SAM3S8/SD8
Synchro.
Error
715
715