AD9648 Analog Devices, AD9648 Datasheet - Page 31

• Manufacturer Part Number: AD9648
• Description: 14-Bit, 125 MSPS/105 MSPS, 1.8 V Dual Analog-to-Digital Converter
• Manufacturer: Analog Devices

Specifications of AD9648

• Resolution (bits): 14bit
• # Chan: 2
• Sample Rate: 125MSPS
• Interface: Par
• Analog Input Type: Diff-Uni
• Ain Range: (2Vref) p-p,2 V p-p
• Adc Architecture: Pipelined
• Pkg Type: CSP

The
port or by asserting the PDWN pin high. In this state, the ADC
typically dissipates less than 2 mW. During power-down, the
output drivers are placed in a high impedance state. Asserting
the PDWN pin low returns the
mode. Note that PDWN is referenced to the digital output
driver supply (DRVDD) and should not exceed that supply
voltage.
Low power dissipation in power-down mode is achieved by
shutting down the reference, reference buffer, biasing networks,
and clock. Internal capacitors are discharged when entering power-
down mode and then must be recharged when returning to normal
operation. As a result, wake-up time is related to the time spent
in power-down mode, and shorter power-down cycles result in
proportionally shorter wake-up times.
When using the SPI port interface, the user can place the ADC
in power-down mode or standby mode. Standby mode allows
the user to keep the internal reference circuitry powered when
faster wake-up times are required. See the Memory Map section
for more details.
DIGITAL OUTPUTS
The
either 1.8 V CMOS or 1.8 V LVDS logic families. The default
output mode is CMOS, with each channel output on separate
busses as shown in Figure 2.
In CMOS output mode, the CMOS output drivers are sized to
provide sufficient output current to drive a wide variety of logic
families. However, large drive currents tend to cause current
glitches on the supplies and may affect converter performance.
Applications requiring the ADC to drive large capacitive loads
or large fanouts may require external buffers or latches.
The CMOS output can also be configured for interleaved CMOS
output mode via the SPI port. In interleaved CMOS mode, the
data for both channels is output onto a single output bus to
reduce the total number of traces required. The timing diagram for
interleaved CMOS output mode is shown in Figure 3.
The interleaved CMOS output mode is enabled globally onto both
output channels via Bit 5 in Register 0x14. The unused channel
output can be disabled by selecting the appropriate Device Index
(Bit 1 or Bit 0) in Register 0x05, then writing a 1 to local (channel
specific) output port disable bit in Register 0x14.
The output data format can be selected to be either offset binary
or twos complement by setting the SCLK/DFS pin when operating
in the external pin mode (see Table 13).
Table 14. Output Data Format
Input (V)
VIN+ − VIN−
VIN+ − VIN−
VIN+ − VIN−
VIN+ − VIN−
VIN+ − VIN−
AD9648
AD9648
is placed in power-down mode either by the SPI
output drivers can be configured to interface with
Condition (V)
< −VREF − 0.5 LSB
= −VREF
= 0
= +VREF − 1.0 LSB
> +VREF − 0.5 LSB
AD9648
to its normal operating
Offset Binary Output Mode
00 0000 0000 0000
00 0000 0000 0000
10 0000 0000 0000
11 1111 1111 1111
11 1111 1111 1111
Rev. 0 | Page 31 of 44
As detailed in the
Speed ADCs via SPI, the data format can be selected for offset
binary, twos complement, or gray code when using the SPI control.
Table 13. SCLK/DFS Mode Selection (External Pin Mode)
Voltage at Pin
AGND
DRVDD
Digital Output Enable Function (OEB)
The
output pins. The three-state mode is enabled through the SPI
interface and can subsequently be controlled using the OEB pin
or through the SPI. Once enabled via SPI (Bit 7) in Register 0x101,
and the OEB pin is low, the output data drivers and DCOs are
enabled. If the OEB pin is high, the output data drivers and
DCOs are placed in a high impedance state. This OEB function
is not intended for rapid access to the data bus. Note that OEB
is referenced to the digital output driver supply (DRVDD) and
should not exceed that supply voltage.
When using the SPI interface, the data outputs and DCO of
each channel can be independently three-stated by using the
output disable bit (Bit 4) in Register 0x14.
TIMING
The
16 clock cycles. Data outputs are available one propagation
delay (t
Minimize the length of the output data lines and loads placed
on them to reduce transients within the AD9648. These
transients can degrade converter dynamic performance.
The lowest typical conversion rate of the
At clock rates below 10 MSPS, dynamic performance can degrade.
Data Clock Output (DCO)
The
intended for capturing the data in an external register. In CMOS
output mode, the data outputs are valid on the rising edge of DCO,
unless the DCO clock polarity has been changed via the SPI. In
LVDS output mode, the DCO and data output switching edges
are closely aligned. Additional delay can be added to the DCO
output using SPI Register 0x17 to increase the data setup time.
In this case, the Channel A output data is valid on the rising
edge of DCO, and the Channel B output data is valid on the
falling edge of DCO. See Figure 2, Figure 3, and Figure 4 for
a graphical timing description of the output modes.
AD9648
AD9648
AD9648
PD
) after the rising edge of the clock signal.
has a flexible three-state ability for the digital
provides latched data with a pipeline delay of
provides two data clock output (DCO) signals
Twos Complement Mode
10 0000 0000 0000
10 0000 0000 0000
00 0000 0000 0000
01 1111 1111 1111
01 1111 1111 1111
SCLK/DFS
Offset binary (default)
Twos complement
AN-877
Application Note, Interfacing to High
AD9648
SDIO/DCS
DCS disabled
DCS enabled (default)
is 10 MSPS.
AD9648
OR
0
1
0
0
1