AD7608 Analog Devices, AD7608 Datasheet - Page 12

• Manufacturer Part Number: AD7608
• Description: 8-Channel DAS with 18-Bit, Bipolar, Simultaneous Sampling ADC
• Manufacturer: Analog Devices

Specifications of AD7608

• Resolution (bits): 18bit
• # Chan: 8
• Sample Rate: 200kSPS
• Interface: Par,Ser,SPI
• Analog Input Type: Diff-Bip
• Ain Range: Bip 10V,Bip 5.0V
• Adc Architecture: SAR
• Pkg Type: QFP

AD7608
Pin No.
11
12
13
14
15
22 to 16
23
24
25
31 to 27
32
33
Type
DI
DI
DI
DO
DO
DO
P
DO
DO
DO
DO/DI
DO/DI
1 2 F 1 1 F
1
Mnemonic
RESET
R D
A A
C S
A A
BUSY
FRSTDATA
DB[6:0]
V
DB7/D
DB8/D
DB[13:9]
DB14
DB15
DRIVE
E E
/ SCLK
E E
A A
OUT
OUT
A
B
Description
Reset Input. When set to logic high, the rising edge of RESET resets the AD7608. Once t
elapsed, the part should receive a RESET pulse after power up. The RESET high pulse should be
typically 100 ns wide. If a RESET pulse is applied during a conversion, the conversion is aborted. If
a RESET pulse is applied during a read, the contents of the output registers resets to all zeros.
Parallel Data Read Control Input when Parallel Interface is Selected (
Serial Interface is Selected (SCLK). When both
bus is enabled.
In parallel mode, two
channel. The first
In serial mode, this pin acts as the serial clock input for data transfers. The
data output lines, D
result. The rising edge of SCLK clocks all subsequent data bits onto the D
outputs. For further information, see the Conversion Control section.
Chip Select. This active low logic input frames the data transfer. When both
in parallel mode, the output bus, DB[15:0], is enabled and the conversion result is output on the
parallel data bus lines. In serial mode, the
the MSB of the serial output data.
Busy Output. This pin transitions to a logic high after both CONVST A and CONVST B rising edges
and indicates that the conversion process has started. The BUSY output remains high until the
conversion process for all channels is complete. The falling edge of BUSY signals that the conversion
data is being latched into the output data registers and is available to be read after a Time t
data read while BUSY is high must be complete before the falling edge of BUSY occurs. Rising edges
on CONVST A or CONVST B have no effect while the BUSY signal is high.
Digital Output. The FRSTDATA output signal indicates when the first channel, V1, is being read back
on either the parallel or serial interface. When the
three-state. The falling edge of
edge of
result from V1 is available on the output data bus. The FRSTDATA output returns to a logic low
following the third falling edge of
as this clocks out the MSB of V1 on D
falling edge. See the Conversion Control section for more details.
Parallel Output Data Bits, DB6 to DB0. When
digital output pins. When
conversion result during the first
SEL = 1, these pins should be tied to GND.
Logic Power Supply Input. The voltage (2.3 V to 5.25 V) supplied at this pin determines the
operating voltage of the interface. This pin is nominally at the same supply as the supply of the host
interface (that is, DSP and FPGA).
Parallel Output Data Bit 7 (DB7)/Serial Interface Data Output Pin (D
pin acts as a three-state parallel digital output pin. When
output DB9 of the conversion result. When
serial conversion data. See the Conversion Control section for further details.
Parallel Output Data Bit 8 (DB8)/Serial Interface Data Output Pin (D
pin acts as a three-state parallel digital output pin. When
output DB10 of the conversion result. When
outputs serial conversion data. See the Conversion Control section for further details.
Parallel Output Data Bits, DB13 to DB9. When
digital output pins. When
conversion result during the first
P AR
A A
Parallel Output Data Bit 14 (DB14). When
output pin. When
first
SEL = 1, this pins should be tied to GND.
Parallel Output Data Bit 15 (DB15). When
output pin. This pin is used to output DB17 of the conversion result during the first
DB1 of the same conversion result during the second
should be tied to GND.
/ SER SEL = 1, these pins should be tied to GND.
E E
A A
R D
A A
E E
A A
pulse and DB0 of the same conversion result during the second
R D
A A
E E
A A
corresponding to the result of V1 then sets the FRSTDATA pin high indicating that the
C S
A A
R D
A A
OUT
E E
A A
and
E E
A A
pulse outputs DB[17:2], the second
Rev. A | Page 12 of 32
A A
R D
A and D
R D
A A
E E
A A
pulses are required to read the full 18 bits of conversion results from each
C S
A A
C S
A A
E E
A A
are low, this pin is used to output DB16 of the conversion result during the
E E
A A
E E
A A
and
and
OUT
C S
A A
B, out of three-state and clocks out the MSB of the conversion
R D
A A
R D
A A
R D
A A
R D
A A
E E
A A
R D
A A
takes FRSTDATA out of three-state. In parallel mode, the falling
E E
A A
E E
A A
E E
A A
E E
A A
OUT
pulse and output 0 during the second
pulse and output zero during the second
are low, these pins are used to output DB8 to DB2 of the
are low, these pins are used to output DB15 to DB11 of the
. In serial mode, FRSTDATA goes high on the falling edge of
E E
A A
A. It returns low on the 18
P AR
A A
P AR
A A
C S
A A
P AR
A A
P AR
A A
E E
A A
P AR
A A
is used to frame the serial read transfer and clock out
/ SER SEL = 0, this pin act as three-state parallel digital
E E
A A
/ SER SEL = 0, this pin acts as three-state parallel digital
E E
A A
P AR
A A
C S
A A
/ SER SEL = 1, this pin functions as D
E E
A A
/ SER SEL = 0, these pins act as three-state parallel
E E
A A
/ SER SEL = 1, this pin functions as D
E E
A A
E E
A A
and
/ SER SEL = 0, these pins act as three-state parallel
E E
A A
C S
A A
E E
A A
input is high, the FRSTDATA output pin is in
R D
A A
R D
A A
E E
A A
R D
A A
E E
A A
are logic low in parallel mode, the output
pulse. When
C S
A A
C S
A A
E E
A A
E E
A A
E E
A A
pulse outputs DB[1:0].
and
and
R D
A A
R D
A A
th
OUT
OUT
SCLK falling edge after the
E E
A A
E E
A A
R D
A A
are low, this pin is used to
are low, this pin is used to
A). When
B). When
P AR
A A
) /Serial Clock Input when the
E E
A A
R D
A A
OUT
C S
A A
/ SER SEL = 1, this pins
E E
A A
E E
A A
R D
A A
pulse. When
A and D
C S
A A
E E
A A
falling edge takes the
E E
A A
E E
A A
R D
A A
and
pulse. When
P AR
A A
P AR
A A
E E
A A
pulse. When
Data Sheet
OUT
/ SER SEL = 0, this
E E
A A
R D
A A
/ SER SEL = 0, this
E E
A A
R D
A A
OUT
OUT
A and outputs
E E
A A
B serial data
E E
A A
are logic low
B and
pulse and
WAKE-UP
P AR
A A
4
P AR
A A
. Any
/ SER
E E
A A
has
C S
A A
/ SER
E E
A A
C S
A A
E E
A A
E E
A A