AD7608 Analog Devices, AD7608 Datasheet - Page 26

• Manufacturer Part Number: AD7608
• Description: 8-Channel DAS with 18-Bit, Bipolar, Simultaneous Sampling ADC
• Manufacturer: Analog Devices

Specifications of AD7608

• Resolution (bits): 18bit
• # Chan: 8
• Sample Rate: 200kSPS
• Interface: Par,Ser,SPI
• Analog Input Type: Diff-Bip
• Ain Range: Bip 10V,Bip 5.0V
• Adc Architecture: SAR
• Pkg Type: QFP

AD7608
DIGITAL FILTER
The AD7608 contains an optional digital first-order sinc filter
that should be used in applications where slower throughput
rates are used or where higher signal-to-noise ratio or dynamic
range is desirable. The oversampling ratio of the digital filter is
controlled using the oversampling pins, OS [2:0] (see Table 8).
OS 2 is the MSB control bit, and OS 0 is the LSB control bit.
Table 8 provides the oversampling bit decoding to select the
different oversample rates. The OS pins are latched on the falling
edge of BUSY. This sets the oversampling rate for the next
conversion (see Figure 45). In addition to the oversampling
function, the output result is decimated to 18-bit resolution.
If the OS pins are set to select an OS ratio of 8, the next
CONVST x rising edge takes the first sample for each channel,
and the remaining seven samples for all channels are taken with
an internally generated sampling signal. These samples are then
averaged to yield an improvement in SNR performance. Table 8
shows typical SNR performance for both the ±10 V and the
±5 V range. As Table 8 indicates, there is an improvement in
SNR as the OS ratio increases. As the OS ratio increases, the
3 dB frequency is reduced, and the allowed sampling frequency
is also reduced. In an application where the required sampling
frequency is 10 kSPS, an OS ratio of up to 16 can be used. In
this case, the application sees an improvement in SNR, but the
input 3 dB bandwidth is limited to ~6 kHz.
The CONVST A and CONVST B pins must be tied/driven
together when oversampling is turned on. When the over-
sampling function is turned on, the BUSY high time for the
conversion process extends. The actual BUSY high time
depends on the oversampling rate selected: the higher
the oversampling rate, the longer the BUSY high, or total
conversion time (see Table 3).
Table 8. Oversample Bit Decoding
OS [2:0]
000
001
010
011
100
101
110
111
1
SNR values taken with a full scale 100 Hz input signal.
OS Ratio
No OS
2
4
8
16
32
64
Invalid
CONVST A,
CONVST B
SNR ±5 V
Range (dB)
90.5
92.5
94.45
96.5
99.1
101.7
103
BUSY
OS x
1
t
OS_SETUP
SNR ±10 V
Range (dB)
91.2
93.4
95.7
98
100.4
102.8
103.5
CONVERSION N
1
Figure 45. OS Pin Timing
OVERSAMPLE RATE
LATCHED FOR CONVERSION N + 1
Rev. A | Page 26 of 32
3 dB BW ±5 V
Range (kHz)
15
15
13.7
10.3
6
3
1.5
t
OS_HOLD
Figure 44 shows that the conversion time extends as the over-
sampling rate is increased, and the BUSY signal lengthens for the
different oversampling rates. For example, a sampling frequency
of 10 kSPS yields a cycle time of 100 µs. Figure 44 shows OS × 2
and OS × 4; for a 10 kSPS example, there is adequate cycle time to
further increase the oversampling rate and yield greater improve-
ments in SNR performance. In an application where the initial
sampling or throughput rate is at 200 kSPS, for example, and
oversampling is turned on, the throughput rate must be reduced
to accommodate the longer conversion time and to allow for the
read. To achieve the fastest throughput rate possible when over-
sampling is turned on, the read can be performed during the
BUSY high time. The falling edge of BUSY is used to update the
output data registers with the new conversion data; therefore, the
reading of conversion data should not occur on this edge.
Figure 44. No Oversampling, Oversampling × 2, and Oversampling × 4 While
CONVST A,
CONVST B
DB[15:0]
DATA:
BUSY
CS
RD
3 dB BW ±10 V
Range (kHz)
22
22
18.5
11.9
6
3
1.5
OS = 0 OS = 2 OS = 4
4µs
CONVERSION N + 1
9µs
Using Read After Conversion
t
CONV
19µs
t
4
t
4
Maximum Throughput
CONVST x Frequency (kHz)
200
100
50
25
12.5
6.25
3.125
t
4
t
CYCLE
Data Sheet