AD7298 Analog Devices, AD7298 Datasheet - Page 16

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AD7298

Manufacturer Part Number
AD7298
Description
8-Channel, 1MSPS, 12-Bit SAR ADC with Temperature Sensor
Manufacturer
Analog Devices
Datasheet

Specifications of AD7298

Resolution (bits)
12bit
# Chan
8
Sample Rate
1MSPS
Interface
SPI
Analog Input Type
SE-Uni
Ain Range
Uni (Vref),Uni 1.0V,Uni 1.25,Uni 2.0V,Uni 2.5V
Adc Architecture
SAR
Pkg Type
CSP

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AD7298
CONTROL REGISTER
The control register of the AD7298 is a 16-bit, write-only register. Data is loaded from the DIN pin of the AD7298 on the falling edge of
SCLK. The data is transferred on the DIN line at the same time that the conversion result is read from the part. The data transferred on
the DIN line corresponds to the AD7298 configuration for the next conversion. This requires 16 serial clocks for every data transfer. Only
the information provided on the first 16 falling clock edges (after the falling edge of CS ) is loaded to the control register. MSB denotes the
first bit in the data stream. The bit functions are outlined in
is all zeros.
Table 7. Control Register Bit Functions
D15
WRITE
Table 8. Control Register Bit Function Description
Bit
D15
D14
D13 to
D6
D4
4 to 3
D2
D1
D0
Table 9. Channel Address Bits
ADD3
0
0
0
0
0
0
0
0
1
1
MSB
D14
REPEAT
Mnemonic
WRITE
REPEAT
CH0 to CH7
T
DONTC
EXT_REF
T
PPD
SENSE
SENSE
AVG
ADD2
0
0
0
0
1
1
1
1
0
0
D13
CH0
Description
The value written to this bit determines whether the subsequent 15 bits are loaded to the control register. If this
bit is a 1, the following 15 bits are written to the control register; if it is a 0, then the remaining 15 bits are not
loaded to the control register and it remains unchanged.
This bit enables the repeated conversion of the selected sequence of channels.
These eight channel selection bits are loaded at the end of the current conversion and select which analog input
channel is to be converted in the next serial transfer, or they may select the sequence of channels for conversion in
the subsequent serial transfers. Each CHX bit corresponds to an analog input channel. A channel or sequence of
channels is selected for conversion by writing a 1 to the appropriate CHX bit/bits. Channel address bits
corresponding to the conversion result are output on DOUT prior to the 12 bits of data. The next channel to be
converted is selected by the mux on the 14
Writing a 1 to this bit enables the temperature conversion. When the temperature sensor is selected for
conversion, the T
progress; the previous conversion result can be read while the temperature conversion is in progress. Once
T
Don’t care.
Writing a Logic 1 to this bit, enables the use of an external reference. The input voltage range for the external
reference is 1 V to 2.5 V. The external reference should not exceed 2.5 V or the device performance is affected.
Writing a 1 to this bit enables the temperature sensor averaging function. When averaging is enabled, the AD7298
internally computes a running average of the conversion results to determine the final T
Temperature Sensor Averaging section for more details). This mode reduces the influence of noise on the final
T
set to start a temperature sensor conversion.
This partial power-down mode is selected by writing a 1 to this bit in the control register. In this mode, some of
the internal analog circuitry is powered down. The AD7298 retains the information in the control register while in
partial power-down mode. The part remains in this mode until a 0 is written to this bit.
SENSE
SENSE
CH1
D12
_BUSY goes low, CS can be brought low 100 ns later to read the T
result. Selecting this feature does not automatically select the T
D11
CH2
ADD1
0
0
1
1
0
0
1
1
0
0
SENSE
D10
CH3
_BUSY pin goes high after the next CS falling edge to indicate that the conversion is in
D9
CH4
D8
CH5
Table 7
Rev. B | Page 16 of 24
ADD0
0
1
0
1
0
1
0
1
0
1
D7
CH6
th
and
SCLK falling edge.
D6
CH7
Table 8
D5
T
. On power-up, the default content of the control register
SENSE
Analog Input Channel
V
V
V
V
V
V
V
V
T
T
SENSE
SENSE
IN0
IN1
IN2
IN3
IN4
IN5
IN6
IN7
D4
DONTC
with averaging enabled
SENSE
SENSE
for conversion. The T
D3
DONTC
conversion result.
D2
EXT_REF
SENSE
result (see the
SENSE
D1
T
SENSE
bit must also be
AVG
D0
PPD
LSB

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