AD9262 Analog Devices, AD9262 Datasheet - Page 24

• Manufacturer Part Number: AD9262
• Description: 16-Bit, 2.5 MHz/5 MHz/10 MHz, 30 MSPS to 160 MSPS Dual Continuous Time Sigma-Delta ADC
• Manufacturer: Analog Devices

Specifications of AD9262

• Resolution (bits): 16bit
• # Chan: 2
• Sample Rate: 160MSPS
• Interface: Par
• Analog Input Type: Diff-Uni
• Ain Range: 2 V p-p
• Adc Architecture: Sigma-Delta
• Pkg Type: CSP

AD9262
In applications where constant tracking of the dc offsets and
quadrature errors are not needed, the algorithms can be
independently frozen to save power. When frozen, the image
and LO leakage (dc) correction are still performed, but changes
are no longer tracked. Register 0x112[5:3] disables the
respective correction when frozen.
The quadrature gain, quadrature phase, and dc correction
algorithms can also be disabled independently for system
debugging or to save power by setting Register 0x112[2:0].
The default configuration on the AD9262 has the QEC and dc
correction blocks disabled, and Register 0x101[6] must be
pulled high to enable the correction blocks. After the QEC is
enabled and a correction value has been calculated, the value
remains active as long as any one of the QEC functions (DC,
gain, or phase correction) is used.
QEC and DC Correction Range
Table 19 gives the minimum and maximum correction ranges
of the algorithms on the AD9262 If the mismatches are greater
than these ranges, an imperfect correction results.
Table 19. QEC and DC Correction Range
Parameter
Gain
Phase
DC
DIGITAL OUTPUTS
Digital Output Format
The AD9262 offers a variety of digital output formats for ease of
system integration. The digital output on each channel consists
of 16 data bits and an output clock signal (DCO) for data latching.
The data bits can be configured for offset binary, twos comple-
ment, or Gray code by writing to Register 0x14[1:0]. In addition,
the voltage swing of the digital outputs can be configured to 3.3 V
TTL levels or a reduced voltage swing of 1.8 V by accessing
Register 0x14[7]. When 3.3 V voltage levels are desirable, the
DRVDD power supply must be set to 3.3 V.
Figure 58. DC Correction Low Frequency Notch Filter 3 dB Bandwidth vs.
60
50
40
30
20
10
0
30
50
Min
−1.1 dB
−1.79 degrees
−6 %
OUTPUT DATA RATE (MSPS)
70
Output Data Rate
90
110
Max
+1.0 dB
+1.79 degrees
+6%
130
150
Rev. A | Page 24 of 32
Interleaved Outputs
The AD9262 has the added feature of interleaving Channel A
and Channel B data onto one 16-bit bus. This feature is availa-
ble for integer values of K
to half values of K
by writing to Register 0x14[5]. The data from both Channel A
and Channel B are interleaved and presented on the Channel A
bus, whereas the Channel B bus is internally grounded. Channel
A is sampled on the falling edge of DCO and Channel B on the
rising edge. The output of Channel A and Channel B can be
interchanged by inverting the DCO clock, Register 0x16[7]. In this
case, Channel B is sampled on the falling edge and Channel A
on the rising edge.
BUS A
BUS B
Overrange (OR) Condition
The ORA and ORB (ORx) pins serve as indicators for an overrange
condition. The ORx pins are triggered by in-band signals that
exceed the full-scale range of the ADC. In addition, the AD9262
possesses out-of-band gain above 10 MHz. Therefore, a large
out-of-band signal may trip an overrange condition.
The ORx pins are synchronous outputs that are updated at the
output data rate. Ideally, ORx should be latched on the falling
edge of DCO to ensure proper setup-and-hold time. However,
because an overrange condition typically extends well beyond one
clock cycle (that is, it does not toggle at the DCO rate) data can
usually be successfully detected on the rising edge of DCO or
monitored asynchronously.
The AD9262 has two trip points that can trigger an overrange
condition: analog and digital. The analog trip point is located in
the modulator ,and the second trip point is in the digital engine.
In normal operation, it is possible for the analog trip point to
toggle the ORx pin for a number of clock cycles as the analog
input approaches full scale. Because the ORx pin is a pulse-width
modulated (PWM) signal, as the analog input increases in ampli-
tude, the duration of overrange pin toggling increases. Eventually,
when the ORx pin is high for an extended period of time, the
ADC is overloaded, whereby there is little correspondence
between analog input and digital output.
The second trip point is in the digital block. If the input signal is
large enough to cause the data bits to clip to its maximum full-
scale level, an overrange condition occurs. The overrange trip
point can be adjusted by specifying a threshold level.
DCO
DCO
A
Figure 59. Interleaved Output Mode
B
OUT
. The interleave function can be accessed
OUT
A
greater than 8 and does not apply
B
A