AD9262 Analog Devices, AD9262 Datasheet - Page 26

• Manufacturer Part Number: AD9262
• Description: 16-Bit, 2.5 MHz/5 MHz/10 MHz, 30 MSPS to 160 MSPS Dual Continuous Time Sigma-Delta ADC
• Manufacturer: Analog Devices

Specifications of AD9262

• Resolution (bits): 16bit
• # Chan: 2
• Sample Rate: 160MSPS
• Interface: Par
• Analog Input Type: Diff-Uni
• Ain Range: 2 V p-p
• Adc Architecture: Sigma-Delta
• Pkg Type: CSP

AD9262
SERIAL PORT INTERFACE (SPI)
The AD9262 serial port interface (SPI) allows the user to configure
the converter for specific functions or operations through a
structured register space provided inside the ADC. This provides
the user added flexibility and customization depending on the
application. Addresses are accessed via the serial port and can
be written to or read from via the port. Memory is organized
into bytes that are further divided into fields, as documented in
the Memory Map section. For detailed operational information,
see the AN-877 Application Note, Interfacing to High Speed
ADCs via SPI.
CONFIGURATION USING THE SPI
As summarized in Table 22, three pins define the SPI of this ADC.
The SCLK pin synchronizes the read and write data presented
to the ADC. The SDIO pin allows data to be sent and read from
the internal ADC memory map registers. The CSB pin is an active
low control that enables or disables the read and write cycles.
Table 22. Serial Port Interface Pins
Pin Name
SCLK
SDIO
CSB
The falling edge of CSB in conjunction with the rising edge of
SCLK determines the start of the framing. Figure 60 and Table 23
provide an example of the serial timing and its definitions.
Other modes involving CSB are available. CSB can be held low
indefinitely to permanently enable the device (this is called
streaming). CSB can stall high between bytes to allow for addi-
tional external timing. When CSB is tied high, SPI functions are
placed in a high impedance mode.
SCLK
SDIO
CSB
DON’T CARE
DON’T CARE
Description
SCLK (serial clock) is the serial shift clock. SCLK
synchronizes serial interface reads and writes.
SDIO (serial data input/output) is an input and
output depending on the instruction being sent
and the relative position in the timing frame.
CSB (chip select bar) is an active low control that
gates the read and write cycles.
t
SS
R/W
t
SDS
W1
W0
t
SDH
t
SHIGH
A12
t
SLOW
A11
Figure 60. Serial Port Interface Timing Diagram
A10
A9
t
Rev. A | Page 26 of 32
SCLK
A8
A7
During an instruction phase, a 16-bit instruction is transmitted.
Data follows the instruction phase, and the length is determined
by the W0 bit and the W1 bit. All data is composed of 8-bit words.
The first bit of each individual byte of serial data indicates whether
a read or write command is issued. This allows the serial data
input/output (SDIO) pin to change direction from an input to
an output.
In addition to word length, the instruction phase determines if
the serial frame is a read or write operation, allowing the serial
port to be used to both program the chip and to read the contents
of the on-chip memory. If the instruction is a readback opera-
tion, performing a readback causes the serial data input/output
(SDIO) pin to change direction from an input to an output at the
appropriate point in the serial frame.
Data can be sent in MSB-first or in LSB-first mode. MSB first is
the default setting on power-up and can be changed via the
configuration register. For more information, see the AN-877
Application Note, Interfacing to High Speed ADCs via SPI.
Table 23. SPI Timing Diagram Specifications
Parameter
t
t
t
t
t
t
t
SDS
SDH
SCLK
SS
SH
SHIGH
SLOW
D5
Description
Setup time between data and rising edge of SCLK
Hold time between data and rising edge of SCLK
Period of the clock
Setup time between CSB and SCLK
Hold time between CSB and SCLK
Minimum period that SCLK should be in a logic
high state
Minimum period that SCLK should be in a logic
low state
D4
D3
D2
D1
D0
t
SH
DON’T CARE
DON’T CARE