AD9649 Analog Devices, AD9649 Datasheet - Page 20

• Manufacturer Part Number: AD9649
• Description: 14-Bit, 20/40/65/80 MSPS, 1.8 V Analog-to-Digital Converter
• Manufacturer: Analog Devices

Specifications of AD9649

• Resolution (bits): 14bit
• # Chan: 1
• Sample Rate: 80MSPS
• Interface: Par
• Analog Input Type: Diff-Uni
• Ain Range: 2 V p-p
• Adc Architecture: Pipelined
• Pkg Type: CSP

AD9649
CLOCK INPUT CONSIDERATIONS
For optimum performance, clock the AD9649 sample clock inputs,
CLK+ and CLK−, with a differential signal. The signal is typi-
cally ac-coupled into the CLK+ and CLK− pins via a transformer
or capacitors. These pins are biased internally (see Figure 46) and
require no external bias.
Clock Input Options
The AD9649 has a very flexible clock input structure. The clock
input can be a CMOS, LVDS, LVPECL, or sine wave signal.
Regardless of the type of signal being used, clock source jitter is
of great concern, as described in the Jitter Considerations section.
Figure 47 and Figure 48 show two preferred methods for clock-
ing the AD9649. The CLK inputs support up to 4× the rated sample
rate when using the internal clock divider feature. A low jitter clock
source is converted from a single-ended signal to a differential
signal using either an RF transformer or an RF balun.
The RF balun configuration is recommended for clock frequen-
cies between 80 MHz and 320 MHz, and the RF transformer is
recommended for clock frequencies from 3 MHz to 200 MHz.
The back-to-back Schottky diodes across the transformer/balun
secondary limit clock excursions into the AD9649 to ~0.8 V p-p
differential.
CLOCK
Figure 48. Balun-Coupled Differential Clock (Up to 4× Rated Sample Rate)
INPUT
CLOCK
Figure 47. Transformer-Coupled Differential Clock (3 MHz to 200 MHz)
INPUT
CLK+
50Ω
0.1µF
50Ω
1nF
Figure 46. Equivalent Clock Input Circuit
1nF
2pF
100Ω
ADT1-1WT, 1:1 Z
Mini-Circuits
XFMR
0.1µF
AVDD
0.9V
®
0.1µF
0.1µF
0.1µF
0.1µF
SCHOTTKY
SCHOTTKY
HSMS2822
HSMS2822
DIODES:
DIODES:
2pF
CLK+
CLK–
CLK–
CLK+
CLK–
ADC
ADC
Rev. 0 | Page 20 of 32
CLOCK
This limit helps prevent the large voltage swings of the clock
from feeding through to other portions of the AD9649 while
preserving the fast rise and fall times of the signal that are critical
to a low jitter performance.
If a low jitter clock source is not available, another option is to
ac couple a differential PECL signal to the sample clock input
pins, as shown in Figure 49. The
AD9513/AD9514/AD9515/AD9516/AD9517
excellent jitter performance.
A third option is to ac couple a differential LVDS signal to the
sample clock input pins as shown in Figure 50. The AD9510/
AD9511/AD9512/AD9513/AD9514/AD9515/AD9516/AD9517
clock drivers offer excellent jitter performance.
In some applications, it may be acceptable to drive the sample
clock inputs with a single-ended 1.8 V CMOS signal. In such
applications, drive the CLK+ pin directly from a CMOS gate, and
bypass the CLK− pin to ground with a 0.1 μF capacitor (see
Figure 51).
Input Clock Divider
The AD9649 contains an input clock divider with the ability
to divide the input clock by integer values of 1, 2, or 4.
CLOCK
CLOCK
CLOCK
CLOCK
INPUT
INPUT
INPUT
INPUT
INPUT
Figure 50. Differential LVDS Sample Clock (Up to 4× Rated Sample Rate)
Figure 49. Differential PECL Sample Clock (Up to 4× Rated Sample Rate)
Figure 51. Single-Ended 1.8 V CMOS Input Clock (Up to 200 MHz)
50kΩ
50kΩ
50Ω
1
50Ω RESISTOR IS OPTIONAL.
0.1µF
1
0.1µF
0.1µF
50kΩ
0.1µF
0.1µF
50kΩ
V
CC
1kΩ
1kΩ
LVDS DRIVER
PECL DRIVER
CMOS DRIVER
AD951x
AD951x
AD951x
240Ω
AD9510/AD9511/AD9512/
OPTIONAL
240Ω
100Ω
0.1µF
100Ω
100Ω
0.1µF
0.1µF
0.1µF
0.1µF
clock drivers offer
0.1µF
CLK+
CLK–
CLK+
CLK–
CLK+
CLK–
ADC
ADC
ADC