AD9649 Analog Devices, AD9649 Datasheet - Page 6

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AD9649

Manufacturer Part Number
AD9649
Description
14-Bit, 20/40/65/80 MSPS, 1.8 V Analog-to-Digital Converter
Manufacturer
Analog Devices
Datasheet

Specifications of AD9649

Resolution (bits)
14bit
# Chan
1
Sample Rate
80MSPS
Interface
Par
Analog Input Type
Diff-Uni
Ain Range
2 V p-p
Adc Architecture
Pipelined
Pkg Type
CSP

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AD9649
DIGITAL SPECIFICATIONS
AVDD = 1.8 V; DRVDD = 1.8 V, maximum sample rate, 2 V p-p differential input, 1.0 V internal reference; AIN = −1.0 dBFS, 50% duty
cycle clock, unless otherwise noted.
Table 3.
Parameter
DIFFERENTIAL CLOCK INPUTS (CLK+, CLK−)
LOGIC INPUTS (SCLK/DFS, MODE, SDIO/PDWN)
LOGIC INPUTS (CSB)
DIGITAL OUTPUTS
1
2
Internal 30 kΩ pull-down.
Internal 30 kΩ pull-up.
Logic Compliance
Internal Common-Mode Bias
Differential Input Voltage
Input Voltage Range
High Level Input Current
Low Level Input Current
Input Resistance
Input Capacitance
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Low Level Input Current
Input Resistance
Input Capacitance
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Low Level Input Current
Input Resistance
Input Capacitance
DRVDD = 3.3 V
DRVDD = 1.8 V
High Level Output Voltage (I
Low Level Output Voltage (I
High Level Output Voltage (I
Low Level Output Voltage (I
I
I
I
I
I
I
I
I
OH
OH
OL
OL
OH
OH
OL
OL
= 1.6 mA
= 50 μA
= 1.6 mA
= 50 μA
= 50 μA
= 0.5 mA
= 50 μA
= 0.5 mA
2
OL
OL
OH
OH
)
)
)
)
1
Temp
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Rev. 0 | Page 6 of 32
GND − 0.3
Min
0.2
−10
−10
8
1.2
0
−50
−10
1.2
0
−10
40
3.29
3.25
1.79
1.75
AD9649-20/AD9649-40/AD9649-65/AD9649-80
Typ
CMOS/LVDS/LVPECL
0.9
10
4
30
2
26
2
Max
3.6
AVDD + 0.2
+10
+10
12
DRVDD + 0.3
0.8
−75
+10
DRVDD + 0.3
0.8
+10
135
0.2
0.05
0.2
0.05
Unit
V
V p-p
V
μA
μA
pF
V
V
μA
μA
pF
V
V
μA
μA
pF
V
V
V
V
V
V
V
V

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