AD9649 Analog Devices, AD9649 Datasheet - Page 29

• Manufacturer Part Number: AD9649
• Description: 14-Bit, 20/40/65/80 MSPS, 1.8 V Analog-to-Digital Converter
• Manufacturer: Analog Devices

Specifications of AD9649

• Resolution (bits): 14bit
• # Chan: 1
• Sample Rate: 80MSPS
• Interface: Par
• Analog Input Type: Diff-Uni
• Ain Range: 2 V p-p
• Adc Architecture: Pipelined
• Pkg Type: CSP

MEMORY MAP REGISTER DESCRIPTIONS
For additional information about functions controlled in
Register 0x00 to Register 0xFF, see the AN-877 Application
Note, Interfacing to High Speed ADCs via SPI.
USR2 (Register 0x101)
Bit 3—Enable GCLK Detect
Normally set high, Bit 3 enables a circuit that detects encode
rates below ~5 MSPS. When a low encode rate is detected, an
internal oscillator, GCLK, is enabled, ensuring the proper oper-
ation of several circuits. If set low, the detector is disabled.
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Bit 2—Run GCLK
Bit 2 enables the GCLK oscillator. For some applications with
encode rates below 10 MSPS, it may be preferable to set this bit
high to supersede the GCLK detector.
Bit 0—Disable SDIO Pull-Down
Bit 0 can be set high to disable the internal 30 kΩ pull-down on
the SDIO pin, which can be used to limit the loading when many
devices are connected to the SPI bus.
AD9649