AD9649 Analog Devices, AD9649 Datasheet - Page 22

• Manufacturer Part Number: AD9649
• Description: 14-Bit, 20/40/65/80 MSPS, 1.8 V Analog-to-Digital Converter
• Manufacturer: Analog Devices

Specifications of AD9649

• Resolution (bits): 14bit
• # Chan: 1
• Sample Rate: 80MSPS
• Interface: Par
• Analog Input Type: Diff-Uni
• Ain Range: 2 V p-p
• Adc Architecture: Pipelined
• Pkg Type: CSP

AD9649
Low power dissipation in power-down mode is achieved by shut-
ting down the reference, reference buffer, biasing networks, and
clock. Internal capacitors are discharged when entering power-
down mode and then must be recharged when returning to normal
operation. As a result, wake-up time is related to the time spent
in power-down mode, and shorter power-down cycles result in
proportionally shorter wake-up times.
When using the SPI port interface, the user can place the ADC
in power-down mode or standby mode. Standby mode allows
the user to keep the internal reference circuitry powered when
faster wake-up times are required. See the Memory Map section for
more details.
DIGITAL OUTPUTS
The AD9649 output drivers can be configured to interface with
1.8 V to 3.3 V CMOS logic families. Output data can also be multi-
plexed onto a single output bus to reduce the total number of traces
required.
The CMOS output drivers are sized to provide sufficient output
current to drive a wide variety of logic families. However, large
drive currents tend to cause current glitches on the supplies and
may affect converter performance.
Applications requiring the ADC to drive large capacitive loads
or large fanouts may require external buffers or latches.
The output data format can be selected to be either offset binary
or twos complement by setting the SCLK/DFS pin when operating
in the external pin mode (see Table 11).
As detailed in the AN-877 Application Note, Interfacing to High
Speed ADCs via SPI, the data format can be selected for offset
binary, twos complement, or gray code when using the SPI control.
Table 11. SCLK/DFS and SDIO/PDWN Mode Selection
(External Pin Mode)
Voltage at Pin
GND
DRVDD
Table 12. Output Data Format
Input (V)
VIN+ − VIN−
VIN+ − VIN−
VIN+ − VIN−
VIN+ − VIN−
VIN+ − VIN−
SCLK/DFS
Offset binary (default)
Twos complement
Condition (V)
< −VREF − 0.5 LSB
= −VREF
= 0
= +VREF − 1.0 LSB
> +VREF − 0.5 LSB
SDIO/PDWN
Normal operation
(default)
Outputs disabled
Offset Binary Output Mode
00 0000 0000 0000
00 0000 0000 0000
10 0000 0000 0000
11 1111 1111 1111
11 1111 1111 1111
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Digital Output Enable Function (OEB)
When using the SPI interface, the data outputs and DCO can be
independently three-stated by using the programmable external
MODE pin. The OEB function of the MODE pin is enabled via
Bits[6:5] of Register 0x08.
If the MODE pin is configured to operate in traditional OEB mode
and the MODE pin is low, the output data drivers and DCOs are
enabled. If the MODE pin is high, the output data drivers and
DCOs are placed in a high impedance state. This OEB function
is not intended for rapid access to the data bus. Note that the
MODE pin is referenced to the digital output driver supply
(DRVDD) and should not exceed that supply voltage.
TIMING
The AD9649 provides latched data with a pipeline delay of eight
clock cycles. Data outputs are available one propagation delay (t
after the rising edge of the clock signal.
Minimize the length of the output data lines and loads placed on
them to reduce transients within the AD9649. These transients may
degrade converter dynamic performance.
The lowest typical conversion rate of the AD9649 is 3 MSPS.
At clock rates below 3 MSPS, dynamic performance may degrade.
Data Clock Output (DCO)
The AD9649 provides a data clock output (DCO) signal that is
intended for capturing the data in an external register. The CMOS
data outputs are valid on the rising edge of DCO, unless the DCO
clock polarity has been changed via the SPI. See Figure 2 for a
graphical timing description.
Twos Complement Mode
10 0000 0000 0000
10 0000 0000 0000
00 0000 0000 0000
01 1111 1111 1111
01 1111 1111 1111
OR
1
0
0
0
1
PD
)