AD7294 Analog Devices, AD7294 Datasheet - Page 28

• Manufacturer Part Number: AD7294
• Description: 12-Bit Monitor and Control System with Multichannel ADC, DACs, Temperature Sensor, and Current Sense
• Manufacturer: Analog Devices

Specifications of AD7294

• Resolution (bits): 12bit
• # Chan: 9
• Sample Rate: 200kSPS
• Interface: I²C/Ser 2-Wire,Ser
• Analog Input Type: Diff-Uni,SE-Uni
• Ain Range: (Vref) p-p,2 V p-p,Uni (Vref),Uni (Vref) x 2
• Adc Architecture: SAR
• Pkg Type: CSP

AD7294
COMMAND REGISTER (0x00)
Writing in the command register puts the part into command
mode. When in command mode, the part cycles through the
selected channels from LSB (D0) to MSB (D7) on each subse-
quent read (see Table 10). A channel is selected for conversion
if a one is written to the desired bit in the command register. On
power-up, all bits in the command register are set to zero. If the
external T
byte, it is not actually requesting a conversion. The result of the
last automatic conversion is output as part of the sequence (see
the Modes of Operation section).
If a command mode conversion is required while the autocycle
mode is active, it is necessary to disable the autocycle mode
before proceeding to the command mode (see the Autocycle
Mode section for more details).
Table 10. Command Register
Bits
Channel
1
Table 11. Result Register (First Read)
MSB
D15
Alert_Flag
Table 12. Result Register (Second Read)
MSB
D7
B7
S.E. indicates single-ended and DIFF indicates differential.
SENSE
MSB
D7
Read out last
result from
T
SENSE
channels are selected in the command register
2
D14
CH
D6
B6
ID2
D6
Read out last
result from
T
1
SENSE
1
D13
CH
D5
B5
ID1
D5
I
SENSE
2
D12
CH
D4
B4
ID0
Rev. H | Page 28 of 48
D4
I
SENSE
1
D11
B11
D3
B3
RESULT REGISTER (0x01)
The result register is a 16-bit read-only register. The conversion
results for the four uncommitted ADC inputs and the two I
channels are stored in the result register for reading.
Bit D14 to Bit D12 are the channel allocation bits, each of which
identifies the ADC channel that corresponds to the subsequent
result (see the ADC Channel Allocation section for more
details). Bit D11 to Bit D0 contain the most recent ADC result.
D15 is reserved as an alert_flag bit. Table 11 lists the contents of
the first byte that is read from the
lists the contents of the second byte read.
D3
V
or
V
(DIFF)
IN
IN
3 (S.E.)
3 − V
IN
2
D10
B10
D2
B2
D2
V
or
V
(DIFF)
IN
IN
2 (S.E.)
2 − V
IN
3
D9
B9
D1
B1
AD7294
D1
V
or
V
(DIFF)
IN
IN
1 (S.E.)
1 − V
results register; Table 12
IN
0
Data Sheet
LSB
D8
B8
LSB
D0
B0
LSB
D0
V
or
V
(DIFF)
IN
IN
0 (S.E.)
0 − V
IN
SENSE
1