AD7294 Analog Devices, AD7294 Datasheet - Page 41

• Manufacturer Part Number: AD7294
• Description: 12-Bit Monitor and Control System with Multichannel ADC, DACs, Temperature Sensor, and Current Sense
• Manufacturer: Analog Devices

Specifications of AD7294

• Resolution (bits): 12bit
• # Chan: 9
• Sample Rate: 200kSPS
• Interface: I²C/Ser 2-Wire,Ser
• Analog Input Type: Diff-Uni,SE-Uni
• Ain Range: (Vref) p-p,2 V p-p,Uni (Vref),Uni (Vref) x 2
• Adc Architecture: SAR
• Pkg Type: CSP

Data Sheet
ALERTS AND LIMITS THEORY
ALERT_FLAG BIT
The alert_flag bit indicates whether the conversion result being
read or any other channel result has violated the limit registers
associated with it. If an alert occurs and the alert_flag bit is set,
the master can read the alert status register to obtain more
information on where the alert occurred.
ALERT STATUS REGISTERS
The alert status registers are 8-bit read/write registers that provide
information on an alert event. If a conversion results in activa-
tion of the ALERT/BUSY pin or the alert_flag bit in the result
register or T
get more information (see Figure 57 for the alert register
structure).
T
* THESE BITS ARE ALWAYS ACTIVE, ALL OTHER BITS CAN BE
Register A (see Table 19) consists of four channels with two status
bits per channel, one corresponding to each of the DATA
DATA
which are the standard voltage inputs. When the content of this
register is read, any bit with a status of 1 indicates a violation of
its associated limit; that is, it identifies the channel and whether
the violation occurred on the upper or lower limit. If a second
alert event occurs on another channel before the content of the
alert register has been read, the bit corresponding to the second
alert event is also set.
Register B (see Table 20) consists of three channels also with
two status bits per channel, representing the specified DATA
and DATA
limit alerts for the current sense inputs. Bit D4 and Bit D5 represent
T
PROGRAMMED TO BE ACTIVE OR NOT AS REQUIRED.
I
I
SENSE
SENSE
SENSE
SENSE
T
T
T
T
I
I
OVER TEMP ALERT*
I
I
SENSE
SENSE
OPEN DIODE FLAG*
SENSE
SENSE
SENSE
SENSE
SENSE
SENSE
V
V
V
V
V
V
V
V
INT HIGH ALERT
IN
IN
IN
IN
IN
IN
IN
IN
INT LOW ALERT
2 OVERRANGE*
1 OVERRANGE*
LOW
3 HIGH ALERT
2 HIGH ALERT
1 HIGH ALERT
0 HIGH ALERT
3 LOW ALERT
2 LOW ALERT
1 LOW ALERT
0 LOW ALERT
2 HIGH ALERT
1 HIGH ALERT
2 HIGH ALERT
1 HIGH ALERT
2 LOW ALERT
1 LOW ALERT
2 LOW ALERT
1 LOW ALERT
RESERVED
RESERVED
limits. It stores the alert event data for V
LOW
SENSE
limits. Bits[D3:D0] correspond to the high and low
registers, the alert status register can be read to
Figure 57. Alert Register Structure
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
REGISTER
REGISTER
REGISTER
ALERT
ALERT
ALERT
A
B
C
OR
ALERT
CONFIGURATION
FLAG
D2 = 1, D1 = 0
REGISTER
IN
3 to V
ALERT/BUSY
HIGH
IN
and
0,
HIGH
Rev. H | Page 41 of 48
the I
During power-up, it is possible for the fault outputs to be trig-
gered, depending on which supply comes up first. Clearing these
bits as part of the initialization routine is recommended on
power-up by writing a 1 to both D4 and D5.
Internal circuitry in the
the D2± input pins for the external temperature sensor are open
circuit. The most significant bit of Register C (see Table 21)
alerts the user when an open diode flag occurs on the external
temperature sensors. If the internal temperature sensor detects
an
perature alert bit, Bit D6 in Register C, is set and the DAC
outputs are set to a high impedance sate. The remaining six
bits in Register 6 store alert event data for T
T
each of the DATA
To clear the full content of any one of the alert registers, write a
code of FF (all ones) to the relevant registers. Alternatively, the
user can write to the respective alert bit in the selected alert
register to clear the alert associated with that bit. The entire
contents of all the alert status registers can be cleared by writing
a 1 to Bit D1 and Bit D2 in the configuration register, as shown
in Table 24. However, this operation then enables the ALERT/
BUSY pin for subsequent conversions.
DATA
The
ALERT/BUSY pin, software via the alert_flag bit, or both,
depending on the configuration) if the result moves outside the
upper or lower limit set by the user.
The DATA
ALERT/BUSY output pin and/or the alert_flag bit in the conver-
sion result register. If the conversion result is greater than the value
in the DATA
stores the lower limit that activates the ALERT/BUSY output pin
and/or the alert_flag bit in the conversion result register. If the
conversion result is less than the value in the DATA
an alert occurs.
An alert associated with either the DATA
register is cleared automatically once the monitored signal is
back in range; that is, the conversion result is between the limits.
The content of the alert register is updated after each conversion.
A conversion is performed every 50 µs in autocycle mode,
so the content of the alert register may change every 50 µs. If
the ALERT pin signals an alert event and the content of the alert
register is not read before the next conversion is complete, the
content of the register may be changed if the signal being
monitored returns between the prespecified limits. In these circum-
stances, the ALERT pin no longer signals the occurrence of an
alert event.
SENSE
AD7294
SENSE
AD7294
INT with two status bits per channel, one corresponding to
HIGH
1 OVERRANGE and I
HIGH
die temperature greater than 150°C, the overtem-
AND DATA
HIGH
signals an alert (in either hardware via the
register stores the upper limit that activates the
HIGH
register, an alert occurs. The DATA
and DATA
AD7294
LOW
SENSE
MONITORING FEATURES
LOW
can alert if either the D1± or
2 OVERRANGE of V
limits.
HIGH
SENSE
or DATA
1, T
LOW
SENSE
AD7294
LOW
REF
LOW
register,
2, and
register
/10.41.