AD7294 Analog Devices, AD7294 Datasheet - Page 35

• Manufacturer Part Number: AD7294
• Description: 12-Bit Monitor and Control System with Multichannel ADC, DACs, Temperature Sensor, and Current Sense
• Manufacturer: Analog Devices

Specifications of AD7294

• Resolution (bits): 12bit
• # Chan: 9
• Sample Rate: 200kSPS
• Interface: I²C/Ser 2-Wire,Ser
• Analog Input Type: Diff-Uni,SE-Uni
• Ain Range: (Vref) p-p,2 V p-p,Uni (Vref),Uni (Vref) x 2
• Adc Architecture: SAR
• Pkg Type: CSP

Data Sheet
SERIAL BUS ADDRESS BYTE
The first byte the user writes to the device is the slave address
byte. Similar to all I
7-bit serial address. The 5 LSBs are user-programmable by the
3 three-state input pins, as shown in Table 34.
In Table 34, H means tie the pin to V
to DGND, and NC refers to a pin left floating. Note that in this
final case, the stray capacitance on the pin must be less than
30 pF to allow correct detection of the floating state; therefore,
any PCB trace must be kept as short as possible.
Table 34. Slave Address Control Using Three-State Input Pins
AS2
L
L
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H
H
NC
NC
NC
NC
NC
NC
NC
NC
NC
AS1
L
L
L
H
H
H
NC
NC
NC
L
L
L
H
H
H
NC
NC
NC
L
L
L
H
H
H
NC
NC
NC
2
C-compatible devices, the
AS0
L
H
NC
L
H
NC
L
H
NC
L
H
NC
L
H
NC
L
H
NC
L
H
NC
L
H
NC
L
H
NC
DRIVE
Slave Address (A6 to A0)
0x61
0x62
0x63
0x64
0x65
0x66
0x67
0x68
0x69
0x6A
0x6B
0x6C
0x6D
0x6E
0x6F
0x70
0x71
0x72
0x73
0x74
0x75
0x76
0x77
0x78
0x79
0x7A
0x7B
, L means tie the pin
AD7294
has a
Rev. H | Page 35 of 48
INTERFACE PROTOCOL
The
Writing a Single Byte of Data to an 8-Bit Register
The alert registers (0x05, 0x06, 0x07), power-down register
(0x0A), channel sequence register (0x08), temperature offset
registers (0x26, 0x27), and the command register (0x00) are
8-bit registers; therefore, only one byte of data can be written to
each. In this operation, the master device sends a byte of data to
the slave device, see Figure 51. To write data to the register, the
command sequence is as follows:
1.
2.
3.
4.
5.
6.
7.
8.
AD7294
The master device asserts a start condition.
The master sends the 7-bit slave address followed by a zero
for the direction bit, indicating a write operation.
The addressed slave device asserts an acknowledge on SDA.
The master sends a register address.
The slave asserts an acknowledge on SDA.
The master sends a data byte.
The slave asserts an acknowledge on SDA.
The master asserts a stop condition to end the transaction.
uses the following I
2
C protocols.
AD7294