AD9640 Analog Devices, AD9640 Datasheet - Page 44

• Manufacturer Part Number: AD9640
• Description: 14-Bit, 80/105/125/150 MSPS, 1.8 V Dual Analog-to-Digital Converter
• Manufacturer: Analog Devices

Specifications of AD9640

• Resolution (bits): 14bit
• # Chan: 2
• Sample Rate: 150MSPS
• Interface: Par
• Analog Input Type: Diff-Uni
• Ain Range: 1 V p-p,2 V p-p
• Adc Architecture: Pipelined
• Pkg Type: CSP

AD9640
Addr
(Hex)
0x0E
0x10
0x14
0x16
0x17
0x18
0x24
0x25
Digital Feature Control
0x100
0x104
0x106
0x107
0x108
0x109
Register
Name
BIST Enable
(Local)
Offset Adjust
(Local)
Output Mode
Clock Phase
Control
(Global)
DCO Output
Delay (Global)
VREF Select
(Global)
BIST Signature
LSB (Local)
BIST Signature
MSB (Local)
Sync Control
(Global)
Fast Detect
Control (Local)
Fine Upper
Threshold
Register 0
(Local)
Fine Upper
Threshold
Register 1
(Local)
Fine Lower
Threshold
Register 0
(Local)
Fine Lower
Threshold
Register 1
(Local)
Bit 7
(MSB)
Open
Open
Drive
strength
0 V to 3.3 V
CMOS or
ANSI
LVDS:
1 V to 1.8 V
CMOS or
reduced:
LVDS
(global)
Invert DCO
clock
Open
Reference voltage selection
SM sync
enable
Open
Open
Open
00 = 1.25 V p-p
01 = 1.5 V p-p
10 = 1.75 V p-p
11 = 2.0 V p-p (default)
Bit 6
Open
Open
Output type
0 = CMOS
1 = LVDS
(global)
Open
Open
Open
Open
Open
Open
Bit 5
Open
Open
Open
Open
Open
Open
Open
Open
Open
Fine Upper Threshold[7:0]
Fine Lower Threshold[7:0]
Bit 4
Open
Output
enable bar
(local)
Open
Open
Open
Open
BIST signature[15:8]
Rev. B | Page 44 of 52
BIST signature[7:0]
Offset adjust in LSBs from +31 to −32
(twos complement format)
Bit 3
Open
Open
Open
Open
(delay = 2500 ps × register value/31)
Open
Fast Detect Mode Select[2:0]
Fine Upper Threshold[12:8]
Fine Lower Threshold[12:8]
Bit 2
Reset BIST
sequence
Output
invert
(local)
Open
Clock
divider next
sync only
DCO clock delay
00000 = 0 ps
00001 = 81 ps
00010 = 161 ps
…
11110 = 2419 ps
11111 = 2500 ps
Input clock divider phase adjust
000 = no delay
001 = 1 input clock cycle
010 = 2 input clock cycles
011 = 3 input clock cycles
100 = 4 input clock cycles
101 = 5 input clock cycles
110 = 6 input clock cycles
Bit 1
Open
Open
Clock
divider
sync
enable
00 = offset binary
01 = twos complement
01 = gray code
11 = offset binary
(local)
Bit 0
(LSB)
BIST enable
Open
Master
sync
enable
Fast detect
enable
Default
Value
(Hex)
0x00
0x00
0x00
0x00
0x00
0xC0
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
Default
Notes/
Comments
Configures the
outputs and
the format of
the data
Allows
selection of
clock delays
into the input
clock divider
Read only
Read only