AD9640 Analog Devices, AD9640 Datasheet - Page 45

• Manufacturer Part Number: AD9640
• Description: 14-Bit, 80/105/125/150 MSPS, 1.8 V Dual Analog-to-Digital Converter
• Manufacturer: Analog Devices

Specifications of AD9640

• Resolution (bits): 14bit
• # Chan: 2
• Sample Rate: 150MSPS
• Interface: Par
• Analog Input Type: Diff-Uni
• Ain Range: 1 V p-p,2 V p-p
• Adc Architecture: Pipelined
• Pkg Type: CSP

Addr
(Hex)
0x10C
0x10D
0x10E
0x10F
0x110
0x111
0x112
0x113
0x114
0x115
0x116
0x117
0x118
0x119
Register
Name
Signal Monitor
DC Correction
Control
(Global)
Signal Monitor
DC Value
Channel A
Register 0
(Global)
Signal Monitor
DC Value
Channel A
Register 1
(Global)
Signal Monitor
DC Value
Channel B
Register 0
(Global)
Signal Monitor
DC Value
Channel B
Register 1
(Global)
Signal Monitor
SPORT Control
(Global)
Signal Monitor
Control
(Global)
Signal Monitor
Period
Register 0
(Global)
Signal Monitor
Period
Register 1
(Global)
Signal Monitor
Period
Register 2
(Global)
Signal Monitor
Result
Channel A
Register 0
(Global)
Signal Monitor
Result
Channel A
Register 1
(Global)
Signal Monitor
Result
Channel A
Register 2
(Global)
Signal Monitor
Result
Channel B
Register 0
(Global)
Bit 7
(MSB)
Open
Open
Open
Open
Complex
power
calculation
mode
enable
Open
Bit 6
DC
correction
freeze
Open
Open
RMS/MS
magnitude
output
enable
Open
Open
Bit 5
Peak
power
output
enable
Open
Open
Signal Monitor Result Channel A[15:8]
Signal Monitor Result Channel A[7:0]
Signal Monitor Result Channel B[7:0]
DC Correction Bandwidth[3:0]
Signal Monitor Period[23:16]
Signal Monitor Period[15:8]
Signal Monitor Period[7:0]
DC Value Channel A[7:0]
DC Value Channel B[7:0]
Bit 4
Threshold
crossing
output
enable
Open
Open
Rev. B | Page 45 of 52
DC Value Channel A[13:8]
DC Value Channel B[13:8]
Bit 3
1 = ms
mode
rms
MS
0 =
01 = divide by 2
10 = divide by 4
11 = divide by 8
00 = undefined
SPORT SMI
CLK divide
Signal Monitor Value Channel A[19:16]
Bit 2
00 = RMS/MS Magnitude
01 = peak power
1x = threshold count
Signal monitor mode
Bit 1
DC
correction
for signal
path
enable
SPORT
SMI SCLK
sleep
Bit 0
(LSB)
DC
correction
for SM
enable
Signal
monitor
SPORT
output
enable
Signal
monitor
enable
Default
Value
(Hex)
0x00
0x04
0x00
0x40
0x00
0x00
AD9640
Default
Notes/
Comments
Read only
Read only
Read only
Read only
In ADC clock
cycles
In ADC clock
cycles
In ADC clock
cycles
Read only
Read only
Read only
Read only