AD7634 Analog Devices, AD7634 Datasheet - Page 10

• Manufacturer Part Number: AD7634
• Manufacturer: Analog Devices

Specifications of AD7634

• Resolution (bits): 18bit
• # Chan: 1
• Sample Rate: 670kSPS
• Interface: Byte,Par,Ser,SPI
• Analog Input Type: Diff-Bip,Diff-Uni
• Ain Range: 10V p-p,20 V p-p,40 V p-p
• Adc Architecture: SAR
• Pkg Type: CSP,QFP

AD7634
Pin No.
22
23
24
25
26
27
28
29
30
31
32
33
34
35
Mnemonic
D11 or
SDCLK
D12 or
SYNC
D13 or
RDERROR
D14 or
HW/SW
D15 or
SCIN
D16 or
SCCLK
D17 or
SCCS
BUSY
TEN
RD
CS
RESET
PD
CNVST
Type
DI/O
DO
DO
DI/O
DI/O
DI/O
DI/O
DO
DI
DI
DI
DI
DI
DI
2
2
1
Description
When MODE[1:0] = 0, 1, or 2, this output is used as Bit 11 of the parallel port data output bus.
When MODE[1:0] = 3, Serial Data Clock. In all serial modes, this pin is used as the serial data clock input
or output, dependent on the logic state of the EXT/INT pin. The active edge where the data SDOUT is
updated depends on the logic state of the INVSCLK pin.
When MODE[1:0] = 0, 1, or 2, this output is used as Bit 12 of the parallel port data output bus.
When MODE[1:0] = 3, Serial Data Frame Synchronization. In serial master mode (MODE[1:0] = 3,
EXT/INT= low), this output is used as a digital output frame synchronization for use with the internal
data clock.
When a read sequence is initiated and INVSYNC = low, SYNC is driven high and remains high while the
SDOUT output is valid.
When a read sequence is initiated and INVSYNC = high, SYNC is driven low and remains low while the
SDOUT output is valid.
When MODE[1:0] = 0, 1, or 2, this output is used as Bit 13 of the parallel port data output bus.
When MODE[1:0] = 3, Serial Data Read Error. In serial slave mode (MODE[1:0] = 3, EXT/INT = high), this
output is used as an incomplete data read error flag. If a data read is started and not completed when
the current conversion is completed, the current data is lost and RDERROR is pulsed high.
When MODE[1:0] = 0, 1, or 2, this output is used as Bit 14 of the parallel port data output bus.
When MODE[1:0] = 3, Serial Configuration Hardware/Software Select. In serial mode, this input is used
to configure the AD7634 by hardware or software. See the Hardware Configuration section and
Software Configuration section.
When HW/SW = low, the AD7634 is configured through software using the serial configuration register.
When HW/SW = high, the AD7634 is configured through dedicated hardware input pins.
When MODE[1:0] = 0, 1, or 2, this output is used as Bit 15 of the parallel port data output bus.
When MODE[1:0] = 3, Serial Configuration Data Input. In serial software configuration mode (HW/SW =
low), this input is used to serially write in, MSB first, the configuration data into the serial configuration
register. The data on this input is latched with SCCLK. See the
When MODE[1:0] = 0, 1, or 2, this output is used as Bit 16 of the parallel port data output bus.
When MODE[1:0] = 3, Serial Configuration Clock. In serial software configuration mode (HW/SW = low),
this input is used to clock in the data on SCIN. The active edge where the data SCIN is updated
depends on the logic state of the INVSCLK pin. See the
When MODE[1:0] = 0, 1, or 2, this output is used as Bit 17 of the parallel port data output bus.
When MODE[1:0] = 3, Serial Configuration Chip Select. In serial software configuration mode
(HW/SW = low), this input enables the serial configuration port. See the
Busy Output. Transitions high when a conversion is started and remains high until the conversion
is completed and the data is latched into the on-chip shift register. The falling edge of BUSY can be
used as a data-ready clock signal. Note that in master read after convert mode (MODE[1:0] = 3,
EXT/INT = low, RDC = low), the busy time changes according to
Input Range Select. Used in conjunction with BIPOLAR per the following:
Input Range
0 V to 5 V
0 V to 10 V
±5 V
±10 V
Read Data. When CS and RD are both low, the interface parallel or serial output bus is enabled.
Chip Select. When CS and RD are both low, the interface parallel or serial output bus is enabled. CS is
also used to gate the external clock in slave serial mode (not used for serial configurable port).
Reset Input. When high, reset the AD7634. Current conversion, if any, is aborted. The falling edge of
RESET resets the data outputs to all zeros (with OB/2C = high) and clears the configuration register. See
the
Power-Down Input. When PD = high, power down the ADC. Power consumption is reduced and
conversions are inhibited after the current one is completed. The digital interface remains active
during power down.
Conversion Start. A falling edge on CNVST puts the internal sample-and-hold into the hold state and
initiates a conversion.
Digital Interface
BIPOLAR
Low
Low
High
High
section. If not used, this pin can be tied to OGND.
Rev. A | Page 10 of 32
TEN
Low
High
Low
High
Software Configuration
Software Configuration
Table 4
Software Configuration
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section.
section.
section.