AD7634 Analog Devices, AD7634 Datasheet - Page 23

• Manufacturer Part Number: AD7634
• Manufacturer: Analog Devices

Specifications of AD7634

• Resolution (bits): 18bit
• # Chan: 1
• Sample Rate: 670kSPS
• Interface: Byte,Par,Ser,SPI
• Analog Input Type: Diff-Bip,Diff-Uni
• Ain Range: 10V p-p,20 V p-p,40 V p-p
• Adc Architecture: SAR
• Pkg Type: CSP,QFP

Digital Output Supply
The OVDD supplies the digital outputs and allows direct interface
with any logic working between 2.3 V and 5.25 V. OVDD should
be set to the same level as the system interface. Sufficient decoup-
ling is required consisting of at least a 10 μF capacitor and a 100 nF
capacitor with the 100 nF capacitor placed as close as possible
to the AD7634.
Power Sequencing
The AD7634 is independent of power supply sequencing and is
very insensitive to power supply variations on AVDD over a wide
frequency range, as shown in Figure 33.
Power Dissipation vs. Throughput
In impulse mode, the AD7634 automatically reduces its power
consumption at the end of each conversion phase. During the
acquisition phase, the operating currents are very low, which allows
a significant power savings when the conversion rate is reduced
(see Figure 34). This feature makes the AD7634 ideal for very
low power, battery-operated applications.
It should be noted that the digital interface remains active even
during the acquisition phase. To reduce the operating digital supply
currents even further, drive the digital inputs close to the power
rails, that is, OVDD and OGND.
1000
100
75
70
65
60
55
50
45
40
35
30
10
1
1
1
PDREF = PDBUF = HIGH
IMPULSE MODE POWER
WARP MODE POWER
Figure 34. Power Dissipation vs. Sample Rate
10
Figure 33. AVDD PSRR vs. Frequency
10
SAMPLING RATE (kSPS)
100
FREQUENCY (kHz)
1000
100
10000
1000
100000
1000000
10000
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Power Down
Setting PD = high powers down the AD7634, thus reducing
supply currents to their minimums, as shown in Figure 23.
When the ADC is in power down, the current conversion
(if any) is completed and the digital bus remains active. To
further reduce the digital supply currents, drive the inputs to
OVDD or OGND.
Power down can also be programmed with the configuration
register. See the Software Configuration section for details. Note
that when using the configuration register, the PD input is a don’t
care and should be tied to either high or low.
CONVERSION CONTROL
The AD7634 is controlled by the CNVST input. A falling edge
on CNVST is all that is necessary to initiate a conversion. A
detailed timing diagram of the conversion process is shown in
Figure 35
by the power-down input, PD, until the conversion is complete.
The
signals.
Although CNVST is a digital signal, it should be designed with
special care with fast, clean edges and levels with minimum
overshoot, undershoot, or ringing.
The CNVST trace should be shielded with ground and a low value
(such as 50 Ω) serial resistor termination should be added close
to the output of the component that drives this line.
For applications where SNR is critical, the CNVST signal should
have very low jitter. This can be achieved by using a dedicated
oscillator for CNVST generation, or by clocking CNVST with a
high frequency, low jitter clock, as shown in
CNVST
MODE
BUSY
CNVST signal operates independently of CS and RD
ACQUIRE
. Once initiated, it cannot be restarted or aborted, even
t
t
3
5
t
Figure 35. Basic Conversion Timing
1
CONVERT
t
7
t
4
t
2
t
6
ACQUIRE
t
8
Figure 27
AD7634
.
CONVERT