AD7634 Analog Devices, AD7634 Datasheet - Page 24

• Manufacturer Part Number: AD7634
• Manufacturer: Analog Devices

Specifications of AD7634

• Resolution (bits): 18bit
• # Chan: 1
• Sample Rate: 670kSPS
• Interface: Byte,Par,Ser,SPI
• Analog Input Type: Diff-Bip,Diff-Uni
• Ain Range: 10V p-p,20 V p-p,40 V p-p
• Adc Architecture: SAR
• Pkg Type: CSP,QFP

AD7634
INTERFACES
DIGITAL INTERFACE
The AD7634 has a versatile digital interface that can be set up as
either a serial or a parallel interface with the host system. The
serial interface is multiplexed on the parallel data bus. The AD7634
digital interface also accommodates 2.5 V, 3.3 V, or 5 V logic. In
most applications, the OVDD supply pin is connected to the host
system interface 2.5 V to 5.25 V digital supply. Finally, by using the
D0/OB/ 2C input pin, both twos complement or straight binary
coding can be used, except for in a 18-bit parallel interface.
Two signals, CS and RD , control the interface. When at least
one of these signals is high, the interface outputs are in high
impedance. Usually, CS allows the selection of each AD7634
in multicircuit applications and is held low in a single AD7634
design. RD is generally used to enable the conversion result on
the data bus.
RESET
The RESET input is used to reset the AD7634. A rising edge on
RESET aborts the current conversion (if any) and tristates the
data bus. The falling edge of RESET resets the AD7634 and clears
the data bus and configuration register. See Figure 36 for the
RESET timing details.
PARALLEL INTERFACE
The AD7634 is configured to use the parallel interface when
the MODE[1:0] pins = 0, 1 or 2 for 18-/16-/8-bit interfaces,
respectively, as detailed in Table 7.
Master Parallel Interface
Data can be continuously read by tying CS and RD low, thus
requiring minimal microprocessor connections. However, in
this mode, the data bus is always driven and cannot be used in
shared bus applications (unless the device is held in RESET).
Figure 37
RESET
CNVST
BUSY
DATA
BUS
details the timing for this mode.
Figure 36. RESET Timing
t
9
t
8
Rev. A | Page 24 of 32
CS = RD = 0
Slave Parallel Interface
In slave parallel reading mode, the data can be read either after
each conversion, which is during the next acquisition phase, or
during the following conversion, as shown in Figure 38 and
Figure 39, respectively. When the data is read during the conver-
sion, it is recommended that it is read-only during the first half
of the conversion phase. This avoids any potential feedthrough
between voltage transients on the digital interface and the most
critical analog conversion circuitry.
CNVST
CNVST,
BUSY
BUSY
DATA
DATA
BUSY
DATA
Figure 39. Slave Parallel Data Timing for Reading (Read During Convert)
BUS
BUS
BUS
Figure 37. Master Parallel Data Timing for Reading (Continuous Read)
Figure 38. Slave Parallel Data Timing for Reading (Read After Convert)
CS
RD
RD
CS = 0
t
t
t
3
12
3
t
12
PREVIOUS CONVERSION DATA
CONVERSION
PREVIOUS
t
CONVERSION
1
t
1
CURRENT
t
13
t
13
t
10
t
4
t
4
t
11
NEW DATA