AD7634 Analog Devices, AD7634 Datasheet - Page 29

• Manufacturer Part Number: AD7634
• Manufacturer: Analog Devices

Specifications of AD7634

• Resolution (bits): 18bit
• # Chan: 1
• Sample Rate: 670kSPS
• Interface: Byte,Par,Ser,SPI
• Analog Input Type: Diff-Bip,Diff-Uni
• Ain Range: 10V p-p,20 V p-p,40 V p-p
• Adc Architecture: SAR
• Pkg Type: CSP,QFP

HARDWARE CONFIGURATION
The AD7634 can be configured at any time with the dedicated
hardware pins WARP, IMPULSE, BIPOLAR, TEN, D0/OB/ 2C ,
and PD for parallel mode (MODE[1:0] = 0, 1, or 2) or serial
hardware mode (MODE[1:0] = 3, HW/ SW = high). Programming
the AD7634 for mode selection and input range configuration
can be done before or during conversion. Like the RESET input,
the ADC requires at least one acquisition time to settle as indi-
cated in
these inputs are high impedance when using the software
configuration mode.
SOFTWARE CONFIGURATION
The pins multiplexed on D[17:14] used for software configura-
tion are: HW/ SW , SCIN, SCCLK, and SCCS . The AD7634 is
programmed using the dedicated write-only serial configurable
port (SCP) for conversion mode, input range selection, output
coding, and power-down using the serial configuration register.
See
The SCP can only be used in serial software mode selected with
MODE[1:0] = 3 and HW/
plexed on the parallel interface.
The SCP is accessed by asserting the port’s chip select, SCCS ,
and then writing SCIN synchronized with SCCLK, which (like
SDCLK) is edge sensitive depending on the state of INVSCLK.
See
figuration register MSB first. The configuration register is an
internal shift register that begins with Bit 8, the START bit. The
9
be used. As indicated in the timing diagram, at least one acquisition
time is required from the 9
bits and are not written to while the SCP is being updated.
The SCP can be written to at any time, up to 40 MHz, and it
is recommended to write to while the AD7634 is not busy con-
verting, as detailed in Figure 47. In this mode, the full 670 kSPS
is not attainable because the time required for SCP access is
(t
required, the SCP can be written to during conversion; however
th
31
SCCLK edge updates the register and allows the new settings to
+ 9 × 1/ SCCLK + t
Table 11
Figure 47
Figure 46
for details of each bit in the configuration register.
for timing details. SCIN is clocked into the con-
. See
8
Table 6
) minimum. If the full throughput is
BIPOLAR,
IMPULSE
SW = low because the port is multi-
th
CNVST
WARP,
BUSY
SCCLK edge. Bits [1:0] are reserved
TEN
for pin descriptions. Note that
t
8
Figure 46. Hardware Configuration Timing
HW/SW = 1
Rev. A | Page 29 of 32
PD = 0
it is not recommended to write to the SCP during the last 600 ns
of conversion (BUSY = high) or performance degradation can
result. In addition, the SCP can be accessed in both serial master
and serial slave read during and read after convert modes.
Note that at power up, the configuration register is undefined.
The RESET input clears the configuration register (sets all bits
to 0), thus placing the configuration to 0 V to 5 V input, normal
mode, and twos complemented output.
Table 11. Configuration Register Description
Bit
8
7
6
5
4
3
2
1
0
Name
START
BIPOLAR
TEN
PD
IMPULSE
WARP
OB/2C
RSV
RSV
Description
START bit. With the SCP enabled (SCCS =
low), when START is high, the first rising edge
of SCCLK (INVSCLK = low) begins to load the
register with the new configuration.
Input Range Select. Used in conjunction with
Bit 6, TEN, per the following:
Input Range
0 V to 5 V
0 V to 10 V
±5 V
±10 V
Input Range Select. See Bit 7, BIPOLAR.
Power Down.
PD = low, normal operation.
PD = high, power down the ADC. The SCP is
accessible while in power-down. To power-up
the ADC, write PD = low on the next configu-
ration setting.
Mode Select. Used in conjunction with Bit 3,
WARP per the following:
Mode
Normal
Impulse
Warp
Normal
Mode Select. See Bit 4, IMPULSE.
Output Coding
OB/2C = low, use twos complement output.
OB/2C = high, use straight binary output.
Reserved.
Reserved.
t
8
WARP
Low
Low
High
High
BIPOLAR
Low
Low
High
High
IMPULSE
Low
High
Low
High
TEN
Low
High
Low
High
AD7634