AD7142 Analog Devices, AD7142 Datasheet - Page 32

• Manufacturer Part Number: AD7142
• Description: Programmable Controller for Capacitance Touch Sensors
• Manufacturer: Analog Devices

Specifications of AD7142

• Resolution (bits): 16bit
• # Chan: 14
• Sample Rate: 250kSPS
• Interface: I²C/Ser 2-Wire,Ser,SPI
• Analog Input Type: Diff-Uni
• Ain Range: ± 2 pF (Delta C)
• Adc Architecture: Sigma-Delta
• Pkg Type: CSP

AD7142
SCLK
SCLK
Reading Data
A read transaction begins when the master writes the command
word to the AD7142 with the read/write bit set to 1. The master
then supplies 16 clock pulses per data-word to be read, and the
AD7142 clocks out data from the addressed register on the SDO
line. The first data-word is clocked out on the first falling edge
of SCLK following the command word, as shown in Figure 48.
SDI
SDO
SDI
CS
CS
NOTES
1. MULTIPLE SEQUENTIAL REGISTERS CAN BE LOADED CONTINUOUSLY.
2. THE FIRST (LOWEST ADDRESS) REGISTER ADDRESS IS WRITTEN, FOLLOWED BY MULTIPLE 16-BIT DATA-WORDS.
3. THE ADDRESS AUTOMATICALLY INCREMENTS WITH EACH 16-BIT DATA-WORD (ALL 16 BITS MUST BE WRITTEN).
4. CS IS HELD LOW UNTIL THE LAST DESIRED REGISTER HAS BEEN LOADED.
5. 16-BIT COMMAND WORD SETTINGS FOR SEQUENTIAL WRITE OPERATION:
NOTES
1. SDI BITS ARE LATCHED ON SCLK RISING EDGES. SCLK CAN IDLE HIGH OR LOW BETWEEN WRITE OPERATIONS.
2. THE 16-BIT CONTROL WORD MUST BE WRITTEN ON SDI: 5 BITS FOR ENABLE WORD, 1 BIT FOR R/W, AND 10 BITS FOR REGISTER ADDRESS.
3. THE REGISTER DATA IS READ BACK ON THE SDO PIN.
4. X DENOTES DON’T CARE.
5. XXX DENOTES HIGH IMPEDANCE THREE-STATE OUTPUT.
6. CS IS HELD LOW UNTIL ALL REGISTER BITS HAVE BEEN READ BACK.
7. 16-BIT COMMAND WORD SETTINGS FOR SINGLE READBACK OPERATION:
CW
CW[15:11] = 11100 (ENABLE WORD)
CW[10] = 0 (R/W)
CW[9:0] = [AD9, AD8, AD7, AD6, AD5, AD4, AD3, AD2, AD1, AD0] (STARTING MSB JUSTIFIED REGISTER ADDRESS)
15
CW[15:11] = 11100 (ENABLE WORD)
CW[10] = 1 (R/W)
CW[9:0] = [AD9, AD8, AD7, AD6, AD5, AD4, AD3, AD2, AD1, AD0] (10-BIT MSB JUSTIFIED REGISTER ADDRESS)
1
XXX
CW
15
t
ENABLE WORD
CW
2
14
1
t
1
2
XXX
ENABLE WORD
CW
14
CW
13
2
3
t
3
XXX
CW
CW
13
12
4
3
CW
11
XXX
CW
12
5
4
R/W
CW
10
16-BIT COMMAND WORD
XXX
CW
6
11
5
CW
9
7
R/W
t
XXX
CW
4
10
CW
16-BIT COMMAND WORD
6
8
8
XXX
CW
STARTING REGISTER ADDRESS
CW
9
7
7
9
XXX
CW
CW
6
8
10
8
Figure 47. Sequential Register Write SPI Timing
Figure 48. Single Register Readback SPI Timing
CW
XXX
5
CW
7
11
t
5
9
CW
4
REGISTER ADDRESS
XXX
CW
12
6
10
CW
Rev. A | Page 32 of 72
3
13
XXX
CW
5
11
CW
2
14
XXX
CW
4
CW
12
1
15
XXX
CW
CW
3
The AD7142 continues to clock out data on the SDO line
provided the master continues to supply the clock signal on
SCLK. The read transaction finishes when the master takes
CS high. If the AD7142 address pointer reaches its maximum
value, then the AD7142 repeatedly clocks out data from the
addressed register. The address pointer does not wrap around.
0
16
13
D15
XXX
CW
2
17
14
DATA FOR STARTING
REGISTER ADDRESS
D14
XXX
CW
18
1
15
XXX
CW
0
16
D15
X
D1
17
31
t
6
D14
X
D0
18
32
D15
D13
16-BIT READBACK DATA
X
33
19
D14
REGISTER ADDRESS
34
DATA FOR NEXT
D2
X
30
D1
47
D1
X
D0
t
8
31
48
t
7
D15
D0
X
49
32
XXX