AD7938-6 Analog Devices, AD7938-6 Datasheet
AD7938-6
Specifications of AD7938-6
Related parts for AD7938-6
AD7938-6 Summary of contents
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... Full shutdown mode: 2 μA maximum 32-lead LFCSP and TQFP packages GENERAL DESCRIPTION The AD7938 12-bit, high speed, low power, successive approximation (SAR) analog-to-digital converter (ADC). The part operates from a single 2 5.25 V power supply and features throughput rates up to 625 kSPS. The part contains a low noise, wide bandwidth, differential track-and-hold amplifier that can handle input frequencies MHz ...
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... Power vs. Throughput Rate ....................................................... 27 Microprocessor Interfacing ....................................................... 27 Application Hints ........................................................................... 29 Grounding and Layout .............................................................. 29 PCB Design Guidelines for Chip Scale Package .................... 29 Evaluating the AD7938-6 Performance .................................. 29 Outline Dimensions ....................................................................... 30 Ordering Guide .......................................................................... 31 Rev Page Data Sheet ...
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... V typ −0.3 to +1.8 V typ V ± REF V ± REF Rev Page AD7938 MHz 625 kSPS CLKIN SAMPLE A Test Conditions/Comments kHz sine wave IN Differential mode Single-ended mode Differential mode Single-ended mode −85 dB typ, differential mode − ...
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... AD7938-6 Parameter 4 DC Leakage Current Input Capacitance REFERENCE INPUT/OUTPUT V Input Voltage 5 REF DC Leakage Current V Output Voltage REFOUT V Temperature Coefficient REFOUT V Noise REF V Output Impedance REF V Input Capacitance REF LOGIC INPUTS Input High Voltage, V INH Input Low Voltage, V INL Input Current ...
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... CLKIN low pulse width. CLKIN high pulse width (10 RISE FALL , quoted in the timing characteristics is the true bus relinquish time of the part and is independent of the 14 Rev Page AD7938-6 = 10MHz 625 kSPS CLKIN SAMPLE A ) and timed from a voltage level of DD ...
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... AD7938-6 ABSOLUTE MAXIMUM RATINGS T = 25°C, unless otherwise noted. A Table 4. Parameter V to AGND/DGND AGND/DGND DRIVE Analog Input Voltage to AGND Digital Input Voltage to DGND DRIVE DD Digital Output Voltage to DGND V to AGND REFIN AGND to DGND 1 Input Current to Any Pin Except Supplies ...
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... CS, RD, and WR. When W/B is low, this pin acts as the high byte enable pin. When HBEN is low, the low byte of data being written to or read from the AD7938 DB0 to DB7. When HBEN is high, the top four bits of the data being written to or read from the AD7938-6 are on DB0 to DB3. When reading from the device, DB4 to DB6 ...
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... W/B Word/Byte Input. When this input is logic high, data is transferred to and from the AD7938-6 in 12-bit words on Pin DB0 to Pin DB11. When this pin is logic low, byte transfer mode is enabled. Data and the channel ID are transferred on Pin DB0 to Pin DB7, and Pin DB8/HBEN assumes its HBEN functionality. Unused data lines when operating in byte transfer mode should be tied off to DGND ...
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... CODE Figure 7. AD7938-6 Typical DNL @ 0.8 DIFFERENTIAL MODE 0.6 0.4 0.2 0 –0.2 –0.4 –0.6 –0.8 –1.0 0 500 1000 1500 2000 2500 3000 CODE Figure 8. AD7938-6 Typical INL @ AD7938-6 = 625kSPS 3500 4000 = 5 V 3500 4000 ...
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... CODES 9000 8000 7000 6000 5000 4000 3000 2000 1000 3 CODES 0 2046 2047 2048 2049 CODE Figure 12. AD7938-6 Histogram of Codes for 10,000 Samples @ with Internal Reference DD 120 DIFFERENTIAL MODE 110 100 200 400 600 800 RIPPLE FREQUENCY (kHz) Figure 13 ...
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... V point the deviation of the first REF + 1 LSB) after the zero-code error has been REF . See Figure 4. REF supply of frequency the ADC output the ADC output. S AD7938-6 to REF , REF . The frequency S and V of IN− ...
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... The AD7938-6 is tested using the CCIF standard where two input frequencies near the top end of the input bandwidth are used. In this case, the second-order terms are usually distanced in frequency from the original sine waves while the third-order terms are usually at a frequency close to the input frequencies ...
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... SHDW register. See Table 10. 0 RANGE This bit selects the analog input range of the AD7938- set to 0, then the analog input range extends from set to 1, the analog input range extends from × V REF 2.5 V reference is used ...
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... Writing to the Control Register to Program the Sequencer The AD7938-6 needs 13 full CLKIN periods to perform a conversion. If the ADC does not receive the full 13 CLKIN periods, the conversion aborts conversion is aborted after applying 12.5 CLKIN periods to the ADC, ensure that a rising ...
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... ADD2 to ADD0, in each prior write operation. This mode of operation reflects the traditional operation of a multichannel ADC, without the sequencer function being used, where each write to the AD7938-6 selects the next channel for conversion This configuration selects the shadow register for programming ...
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... ADC can progress and cycle with each consecutive falling edge of CONVST . The analog input range for the AD7938 × V depending on the status of the RANGE bit in the control REF register ...
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... Twos Complement Output Coding and 2 × V TYPICAL CONNECTION DIAGRAM Figure 18 shows a typical connection diagram for the AD7938-6. The AGND and DGND pins are connected together at the device for good noise suppression. The V is decoupled to AGND with a 0.47 μF capacitor to avoid noise pickup if the internal reference is used ...
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... V being preconditioned before it is applied to the AD7938-6. In cases where the analog input amplitude is ±2.5 V, the 3R resistor can be replaced with a resistor of value R. The resultant voltage on the analog input of the AD7938 signal ranging from this case, 1k 10k the 2 × ...
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... Using an Op Amp Pair An op amp pair can be used to directly couple a differential signal to one of the analog input pairs of the AD7938-6. The circuit configurations shown in Figure 27 and Figure 28 show how a dual op amp can be used to convert a single-ended signal to ...
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... Figure 28. Dual Op Amp Circuit to Convert a Single-Ended Unipolar Signal into a Differential Signal Another method of driving the AD7938 use the (or equivalent) differential amplifier. The AD8138 can be used as a single-ended-to-differential amplifier differential-to- differential amplifier. The device is as easy to use amp and greatly simplifies differential signal amplification and driving ...
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... SEQ and SHDW bits are set avoid interrupting the conversion sequence. The sequence program remains in force until such time as the AD7938-6 is written to and the SEQ and SHDW bits are configured with any bit combination except 1, 0. shows a flow chart of the programmable sequence operation. ...
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... Figure 34. Typical V Connection Diagram REF Digital Inputs range cannot be used. The digital inputs applied to the AD7938-6 are not limited by the maximum ratings that limit the analog inputs. Instead, the digital inputs applied can and are not restricted by the + V ≤ V REF IN− ...
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... DB0 TO DB11 WITH CS AND RD TIED LOW DB0 TO DB11 Figure 35. AD7938-6 Parallel Interface—Conversion and Read Cycle Timing in Word Mode ( the end of the conversion, BUSY goes low and can be used to activate an interrupt service routine. The CS and RD lines are then activated in parallel to read the 12 bits of conversion data. ...
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... AD7938-6. HBEN/DB8 CS RD DB0 TO DB7 Figure 36. AD7938-6 Parallel Interface—Read Cycle Timing for Byte Mode Operation ( The data is placed onto the data bus a time, t and RD go low. The RD rising edge can be used to latch data out of the device. After a time, t three-stated. ...
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... Figure 37 shows the write cycle timing diagram of the AD7938-6 in word mode. When operating in word mode, the HBEN input DB0 TO DB11 Figure 37. AD7938-6 Parallel Interface—Write Cycle Timing for Word Mode Operation ( HBEN/DB8 CS WR DB0 TO DB11 Figure 38. AD7938-6 Parallel Interface— ...
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... Point A in Figure 35. When this mode is entered, all circuitry on the AD7938-6 is powered down except for the reference and reference buffer. The track-and-hold goes into hold at this point also and remains in hold as long as the device is in standby. The part remains in standby until the next rising edge of CONVST powers up the device ...
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... If the maximum CLKIN frequency of 10 MHz is used, the conversion time accounts for only 1.315 μs of the overall cycle time while the AD7938-6 remains in standby mode for the remainder of the cycle external reference is used, the power-up time reduces to 600 ns ...
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... I/O spaces. Each data transfer consumes two bus cycles, one cycle to fetch data and the other to store data. After the AD7938-6 has finished a conversion, the BUSY line generates a DMA request to Channel 1 (DRQ1). Because of the interrupt, the processor performs a DMA read operation that also resets the interrupt latch ...
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... AD7938-6 as possible. Avoid running digital lines under the device as this couples noise onto the die. The analog ground plane should be allowed to run under the AD7938-6 to avoid noise coupling. The power supply lines to the AD7938-6 should use as large a trace as possible to provide low impedance paths and reduce the effects of glitches on the power supply line ...
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... AD7938-6 OUTLINE DIMENSIONS PIN 1 INDICATOR 12° MAX 1.00 0.85 0.80 SEATING PLANE 1.05 1.00 0.95 0.15 0.05 VIEW A ROTATED 90° CCW 5.00 BSC SQ 0.60 MAX 24 0.50 4.75 BSC BSC SQ 17 0.50 TOP VIEW 0.40 0.80 MAX 0.30 0.65 TYP 0.05 MAX 0.02 NOM COPLANARITY 0.30 0.08 0.25 0.20 REF 0.18 COMPLIANT TO JEDEC STANDARDS MO-220-VHHD-2 Figure 46. 32-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 5 × Body, Very Thin Quad ...
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... AD7938BSUZ-6REEL7 –40°C to +85° RoHS Compliant Part. 2 Linearity error here refers to integral linearity error. 2 Linearity Error (LSB) Package Description ±1 32-Lead LFCSP_VQ ±1 32-Lead LFCSP_VQ ±1 32-Lead TQFP ±1 32-Lead TQFP Rev Page AD7938-6 Package Option CP-32-2 CP-32-2 SU-32-2 SU-32-2 ...
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... AD7938-6 NOTES ©2004–2011 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D04751-0-10/11(C) Rev Page Data Sheet ...