AD7938-6 Analog Devices, AD7938-6 Datasheet - Page 28

• Manufacturer Part Number: AD7938-6
• Description: 8-Channel, 625 kSPS, 12-Bit Parallel ADCs with a Sequencer
• Manufacturer: Analog Devices

Specifications of AD7938-6

• Resolution (bits): 12bit
• # Chan: 8
• Sample Rate: 625kSPS
• Interface: Par
• Analog Input Type: Diff-Uni,SE-Uni
• Ain Range: Uni (Vref),Uni (Vref) x 2
• Adc Architecture: SAR
• Pkg Type: CSP,QFP

AD7938-6
AD7938-6 to ADSP-21065L Interface
Figure 43 shows a typical interface between the AD7938-6 and
the
example of one of three DMA handshake modes. The MS
control line is actually three memory select lines. Internal
ADDR
asserted as chip selects. The DMAR
this setup as the interrupt to signal the end of conversion. The
rest of the interface is a standard handshaking operation.
AD7938-6 to TMS32020, TMS320C25, and TMS320C5x
Interface
Parallel interfaces between the AD7938-6 and the TMS32020,
TMS320C25, and TMS320C5x family of DSPs are shown in
Figure 44. The memory mapped address chosen for the AD7938-6
should be chosen to fall in the I/O memory space of the DSPs.
The parallel interface on the AD7938-6 is fast enough to
interface to the TMS32020 with no extra wait states. If high
speed glue logic, such as 74AS devices, is used to drive the RD
and the WR lines when interfacing to the TMS320C25, then
again, no wait states are necessary. However, if slower logic is
used, data accesses may be slowed sufficiently when reading
from, and writing to, the part to require the insertion of one
wait state. Extra wait states are necessary when using the
TMS320C5x at their fastest clock speeds (see the TMS320C5x
User’s Guide for details).
Data is read from the ADC using the following instruction
where:
D is the data memory address.
ADC is the AD7938-6 address.
*ADDITIONAL PINS REMOVED FOR CLARITY.
ADSP-21065L*
ADSP-21065L
IN D, ADC
25 to 24
A0 TO A23
D0 TO D31
DMAR
are decoded into MS
MS
WR
RD
X
1
Figure 43. Interfacing to the ADSP-21065L
SHARC® processor. This interface is an
ADDRESS BUS
ADDRESS
ADDRESS
DECODER
DATA BUS
LATCH
ADDRESS BUS
3 to 0
1
, these lines are then
(DMA request 1) is used in
DSP/USER SYSTEM
CS
BUSY
RD
WR
DB0 TO DB11
AD7938-6*
CONVST
x
Rev. C | Page 28 of
*ADDITIONA
AD7938-6 to 80C186 Interface
Figure 45 shows the AD7938-6 interfaced to the 80C186
microprocessor. The 80C186 DMA controller provides two
independent high speed DMA channels where data transfer
can occur between memory and I/O spaces. Each data transfer
consumes two bus cycles, one cycle to fetch data and the other
to store data. After the AD7938-6 has finished a conversion, the
BUSY line generates a DMA request to Channel 1 (DRQ1).
Because of the interrupt, the processor performs a DMA read
operation that also resets the interrupt latch. Sufficient priority
must be assigned to the DMA channel to ensure that the DMA
request is serviced before the completion of the next
conversion.
*ADDITIONAL PINS OMITTED FOR CLARITY.
32
DMD0 TO DMD15
TMS320C50*
TMS320C25/
TMS32020/
80C186*
AD0 TO AD15
Figure 44. Interfacing to the TMS32020/TMS320C25/TMS320C5x
A16 TO A19
A0 TO A15
L PINS OMITTED FOR CLARITY
READY
DRQ1
STRB
ALE
MSC
INT
WR
RD
R/W
IS
X
ADDRESS/DATA BUS
Figure 45. Interfacing to the 80C186
EN
DECODER
ADDRESS BUS
ADDRESS
ADDRESS
Q R
LATCH
S
ADDRESS
DECODER
ADDRESS BUS
DATA BUS
TMS320C25
ONLY
DATA BUS
DSP/USER SYSTEM
DB11 TO DB0
CS
WR
RD
BUSY
Data Sheet
AD7938-6*
MICROPROCESSOR/
DB0 TO DB11
CS
BUSY
RD
WR
CONVST
USER SYSTEM
AD7938-6*
CONVST