AD7938 Analog Devices, AD7938 Datasheet
AD7938
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AD7938 Summary of contents
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... Full shutdown mode: 2 µA maximum 32-lead LFCSP and TQFP packages GENERAL DESCRIPTION The AD7938/AD7939 are 12-bit and 10-bit, high speed, low power, successive approximation (SAR) analog-to-digital converters (ADCs). The parts operate from a single 2 5.25 V power supply and feature throughput rates ...
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... On-Chip Registers .......................................................................... 15 Control Register .......................................................................... 15 Sequencer Operation ................................................................. 16 Shadow Register .......................................................................... 17 REVISION HISTORY 10/11—Rev Rev. C Changes to SINAD Specification in Features Section ................. 1 Changes to AD7938 Specifications Section .................................. 3 Updated Outline Dimensions ....................................................... 32 Changes to Ordering Guide .......................................................... 33 2/07—Rev Rev. B Updated Format .................................................................. Universal Changes to Sequencer Operation Section ................................... 16 Updated Outline Dimensions ....................................................... 32 7/05— ...
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... Data Sheet SPECIFICATIONS AD7938 SPECIFICATIONS 2 5.25 V, internal/external V DD DRIVE unless otherwise noted. A MIN MAX Table 2. Parameter DYNAMIC PERFORMANCE 2 Signal-to-Noise and Distortion (SINAD) 2 Signal-to-Noise Ratio (SNR) 2 Total Harmonic Distortion (THD) 2 Peak Harmonic or Spurious Noise (SFDR) 2 Intermodulation Distortion (IMD) ...
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... AD7938/AD7939 Parameter REFERENCE INPUT/OUTPUT V Input Voltage 5 REF DC Leakage Current V Output Voltage REFOUT V Temperature Coefficient REFOUT V Noise REF V Output Impedance REF V Input Capacitance REF LOGIC INPUTS Input High Voltage, V INH Input Low Voltage, V INL Input Current Input Capacitance LOGIC OUTPUTS ...
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... REF V ± REF ±1 µA max 45 pF typ 10 pF typ Rev Page AD7938/AD7939 = 25.5 MHz 1.5 MSPS; CLKIN SAMPLE Test Conditions/Comments kHz sine wave IN Differential mode Single-ended mode kHz kHz kHz 300 kHz IN NOISe @ ...
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... AD7938/AD7939 Parameter REFERENCE INPUT/OUTPUT V Input Voltage 5 REF DC Leakage Current 4 V Output Voltage REFOUT V Temperature Coefficient REFOUT V Noise REF V Output Impedance REF V Input Capacitance REF LOGIC INPUTS Input High Voltage, V INH Input Low Voltage, V INL Input Current Input Capacitance LOGIC OUTPUTS ...
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... CLKIN low pulse width. CLKIN high pulse width (10 RISE FALL , quoted in the timing characteristics is the true bus relinquish time of the part and is independent of the 14 Rev Page AD7938/AD7939 = 25.5 MHz 1.5 MSPS SAMPLE A ) and timed from a voltage level ...
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... AD7938/AD7939 ABSOLUTE MAXIMUM RATINGS T = 25°C, unless otherwise noted. A Table 5. Parameter V to AGND/DGND AGND/DGND DRIVE Analog Input Voltage to AGND Digital Input Voltage to DGND DRIVE DD Digital Output Voltage to DGND V to AGND REFIN AGND to DGND Input Current to Any Pin Except Supplies ...
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... CS, RD, and WR. When W/B is low, this pin acts as the high byte enable pin. When HBEN is low, the low byte of data being written to or read from the AD7938/AD7939 is on DB0 to DB7. When HBEN is high, the top four bits of the data being written to or read from the AD7938/AD7939 are on DB0 to DB3. When reading from the device, DB4 to DB6 of the high byte contains the ID of the channel to which the conversion result corresponds (see the channel address bits in Table 10) ...
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... W/B Word/Byte Input. When this input is logic high, data is transferred to and from the AD7938/AD7939 in 12-bit/10-bit words on the DB0/DB2 to DB11 pins. When this pin is logic low, byte transfer mode is enabled. Data and the channel ID are transferred on Pin DB0 to Pin DB7, and Pin DB8/HBEN assumes its HBEN functionality. Unused data lines when operating in byte transfer mode should be tied off to DGND ...
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... F = 1.5MSPS SAMPLE RANGE = REF DIFFERENTIAL MODE 20 0 100 200 300 400 500 600 FREQUENCY (kHz) Figure 6. AD7938 SINAD vs. Analog Input Frequency for Various Supply Voltages DRIVE 810 1010 500 600 700 800 700 800 900 1000 Rev Page ...
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... CODES 9000 8000 7000 6000 5000 4000 3000 2000 1000 3 CODES 0 2046 2047 2048 2049 CODE Figure 13. AD7938 Histogram of Codes for 10k Samples @ with the Internal Reference DD 120 DIFFERENTIAL MODE 110 100 200 400 600 800 RIPPLE FREQUENCY (kHz) Figure 14 ...
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... Pf is the power at frequency f in the ADC output the power at frequency f S Rev Page AD7938/AD7939 input range with −V REF biased about the V point the deviation of the first REF + 1 LSB) after the zero-code error has been adjusted out. ...
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... The AD7938/AD7939 are tested using the CCIF standard where two input frequencies near the top end of the input bandwidth are used. In this case, the second-order terms are usually ...
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... SHDW register. See Table 11. 0 RANGE This bit selects the analog input range of the AD7938/AD7939 set to 0, the analog input range extends from set to 1, the analog input range extends from × V REF 2.5 V reference is used ...
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... ADD2 to ADD0, in each prior write operation. This mode of operation reflects the traditional operation of a multichannel ADC, without the sequencer function being used, where each write to the AD7938/AD7939 selects the next channel for conversion This configuration selects the shadow register for programming ...
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... Data Sheet SHADOW REGISTER The shadow register on the AD7938/AD7939 is an 8-bit, write- only register. Data is loaded from DB0 to DB7 on the rising edge The eight LSBs load into the shadow register. The information is written into the shadow register provided that the SEQ and SHDW bits in the control register were set to 0 and 1, respectively, in the previous write to the control register ...
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... ADC can progress and cycle with each consecutive falling edge of CONVST . The analog input range for the AD7938/AD7939 × depending on the status of the RANGE bit in REF the control register ...
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... Figure 18. AD7938/AD7939 Ideal Transfer Characteristic with Twos Complement Output Coding and 2 × V TYPICAL CONNECTION DIAGRAM Figure 19 shows a typical connection diagram for the AD7938/AD7939. The AGND and DGND pins are connected together at the device for good noise suppression. The V /V pin is decoupled to AGND with a 0.47 μF ...
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... V being preconditioned before it is applied to the AD7938/AD7939. In cases where the analog input amplitude is ±2.5 V, the 3R resistor can be replaced with a resistor of value R. The resultant voltage on the analog input of the AD7938/AD7939 is a signal ranging from this case, the 2 × +1.25V 0V – ...
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... When a conversion takes place, the common mode is rejected, resulting in a virtually noise-free signal of amplitude − corresponding to the digital codes 4096 for the REF AD7938 and 0 to 1024 for the AD7939. If the 2 × V used, the input signal amplitude extends from −2 V after conversion. 3 25° ...
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... Figure 29. Dual Op Amp Circuit to Convert a Single-Ended Unipolar Signal into a Differential Signal Another method of driving the AD7938/AD7939 is to use the AD8138 differential amplifier. The AD8138 can be used as a single-ended-to-differential amplifier differential-to- differential amplifier. The device is as easy to use amp and greatly simplifies differential signal amplification and driving ...
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... SEQ and SHDW bits are set avoid interrupting the conversion sequence. The sequence program remains in force until such time as the AD7938/AD7939 is written to and the SEQ and SHDW bits are configured with any bit combination except 1, 0. Figure 32 shows a flow chart of the programmable sequence operation ...
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... REF IN− DD voltage at which the parallel interface operates. V ADC to easily interface and 5 V processors. For example, if the AD7938/AD7939 are operated with and the V AD7938/AD7939 have better dynamic performance with while still being able to interface directly processors ...
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... DB0 TO DB11 WITH CS AND RD TIED LOW DB0 TO DB11 Figure 36. AD7938/AD7939 Parallel Interface—Conversion and Read Cycle Timing in Word Mode ( the end of the conversion, BUSY goes low and can be used to activate an interrupt service routine. The CS and RD lines are then activated in parallel to read the 12- or 10-bits of conversion data ...
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... CS RD DB0 TO DB7 Figure 37. AD7938/AD7939 Parallel Interface—Read Cycle Timing for Byte Mode Operation ( The CS and RD signals are gated internally and the level is triggered active low. In either word mode or byte mode, CS and RD can be tied together because the timing specifications for t and t are 0 ns minimum ...
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... HBEN/DB8 CS WR DB0 TO DB11 Figure 39. AD7938/AD7939 Parallel Interface—Write Cycle Timing for Byte Mode Operation ( Figure 38 shows the write cycle timing diagram of the AD7938/AD7939 in word mode. When operating in word mode, the HBEN input does not exist and only one write operation is required to write the word of data to the device ...
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... Point A in Figure 36. When this mode is entered, all circuitry on the AD7938/AD7939 is powered down except for the reference and reference buffer. The track-and-hold goes into hold at this point also and remains in hold as long as the device is in standby ...
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... DD Figure 43 shows the AD7938/AD7939 interfaced to the ADSP- 21xx series of DSPs as a memory-mapped device. A single wait state may be necessary to interface the AD7938/AD7939 to the ADSP-21xx depending on the clock speed of the DSP. The wait state can be programmed via the data memory wait state control register of the ADSP-21xx (see the ADSP-21xx family = 3 V ...
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... Parallel interfaces between the AD7938/AD7939 and the TMS32020, TMS320C25, and TMS320C5x family of DSPs are shown in Figure 45. The memory mapped address chosen for the AD7938/AD7939 should be chosen to fall in the I/O memory space of the DSPs. The parallel interface on the AD7938/AD7939 is fast enough to interface to the TMS32020 with no extra wait states ...
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... The analog ground plane should be allowed to run under the AD7938/AD7939 to avoid noise coupling. The power supply lines to the AD7938/AD7939 should use as large a trace as possible to provide low impedance paths and reduce the effects of glitches on the power supply line. ...
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... AD7938/AD7939 OUTLINE DIMENSIONS PIN 1 INDICATOR 12° MAX 1.00 0.85 0.80 SEATING PLANE 1.05 1.00 0.95 0.15 0.05 VIEW A ROTATED 90° CCW 5.00 BSC SQ 0.60 MAX 24 0.50 4.75 BSC BSC SQ 17 0.50 TOP VIEW 0.40 0.80 MAX 0.30 0.65 TYP 0.05 MAX 0.02 NOM COPLANARITY 0.30 0.08 0.20 REF 0.25 0.18 COMPLIANT TO JEDEC STANDARDS MO-220-VHHD-2 Figure 47. 32-Lead Lead Frame Chip Scale Package [LFCSP_VQ × Body, Very Thin Quad ...
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... AD7938BCPZ –40°C to +85°C AD7938BCPZ-REEL7 –40°C to +85°C AD7938BSUZ –40°C to +85°C AD7938BSUZ-REEL7 –40°C to +85°C EVAL-AD7938CBZ AD7939BCPZ –40°C to +85°C AD7939BCPZ-REEL7 –40°C to +85°C AD7939BSUZ –40°C to +85°C AD7939BSUZ-REEL7 –40°C to +85° RoHS Compliant Part ...
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... AD7938/AD7939 NOTES Rev Page Data Sheet ...
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... Data Sheet NOTES Rev Page AD7938/AD7939 ...
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... AD7938/AD7939 NOTES ©2004–2011 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D03715-0-10/11(C) Rev Page Data Sheet ...