AD7938 Analog Devices, AD7938 Datasheet - Page 16

• Manufacturer Part Number: AD7938
• Description: 8-Channel, 1.5 MSPS, 12-Bit Parallel ADCs with a Sequencer
• Manufacturer: Analog Devices

Specifications of AD7938

• Resolution (bits): 12bit
• # Chan: 8
• Sample Rate: 1.5MSPS
• Interface: Byte,Par
• Analog Input Type: Diff-Uni,SE-Uni
• Ain Range: (2Vref) p-p,5V p-p,Uni (Vref),Uni (Vref) x 2,Uni 2.5V,Uni 5.0V
• Adc Architecture: SAR
• Pkg Type: CSP,QFP

AD7938/AD7939
SEQUENCER OPERATION
The configuration of the SEQ and SHDW bits in the control
register allows the user to select a particular mode of operation
of the sequencer function. Table 11 outlines the four modes of
operation of the sequencer.
Writing to the Control Register to Program the Sequencer
The AD7938/AD7939 need 13 full CLKIN periods to perform a
conversion. If the ADC does not receive the full 13 CLKIN
Table 10. Analog Input Type Selection
Channel Address
ADD2
0
0
0
0
1
1
1
1
Table 11. Sequence Selection
SEQ
0
0
1
1
SHDW
0
1
0
1
ADD1
0
0
1
1
0
0
1
1
ADD0
0
1
0
1
0
1
0
1
Sequence Type
This configuration is selected when the sequence function is not used. The analog input channel selected on each
individual conversion is determined by the contents of the channel address bits, ADD2 to ADD0, in each prior write
operation. This mode of operation reflects the traditional operation of a multichannel ADC, without the sequencer function
being used, where each write to the AD7938/AD7939 selects the next channel for conversion.
This configuration selects the shadow register for programming. The following write operation loads the data on DB0 to
DB7 to the shadow register. This programs the sequence of channels to be converted continuously after each CONVST
falling edge. See the Shadow Register section and Table 12.
If the SEQ and SHADOW bits are set in this way, the sequence function is not interrupted upon completion of the write
operation. This allows other bits in the control register to be altered between conversions while in a sequence without
terminating the cycle.
This configuration is used in conjunction with the channel address bits (ADD2 to ADD0) to program continuous
conversions on a consecutive sequence of channels from Channel 0 through to a selected final channel as determined by
the channel address bits in the control register.
MODE0 = 0, MODE1 = 0
Eight Single-Ended
Input Channels
V
V
V
V
V
V
V
V
V
IN
IN
IN
IN
IN
IN
IN
IN
IN+
0
1
2
3
4
5
6
7
V
AGND
AGND
AGND
AGND
AGND
AGND
AGND
AGND
IN−
MODE0 = 0, MODE1 = 1
Four Fully Differential
Input Channels
V
V
V
V
V
V
V
V
V
IN
IN
IN
IN
IN
IN
IN
IN
IN+
0
1
2
3
4
5
6
7
Rev. C | Page 16 of 36
V
V
V
V
V
V
V
V
V
IN
IN
IN
IN
IN
IN
IN
IN
IN−
1
0
3
2
5
4
7
6
periods, the conversion aborts. If a conversion is aborted after
applying 12.5 CLKIN periods to the ADC, ensure that a rising
edge of CONVST or a falling edge of CLKIN is applied to the
part before writing to the control register to program the
sequencer. If these conditions are not met, the sequencer will
not be in the correct state to handle being reprogrammed for
another sequence of conversions and the performance of the
converter is not guaranteed.
MODE0 = 1, MODE1 = 0
Four Pseudo Differential Input
Channels (Pseudo Mode 1)
V
V
V
V
V
V
V
V
V
IN
IN
IN
IN
IN
IN
IN
IN
IN+
0
1
2
3
4
5
6
7
V
V
V
V
V
V
V
V
V
IN
IN
IN
IN
IN
IN
IN
IN
IN−
1
0
3
2
5
4
7
6
MODE0 = 1, MODE1 = 1
Seven Pseudo Differential Input
Channels (Pseudo Mode 2)
V
V
V
V
V
V
V
V
IN
IN
IN
IN
IN
IN
IN
IN+
0
1
2
3
4
5
6
Not Allowed
Data Sheet
V
V
V
V
V
V
V
V
IN
IN
IN
IN
IN
IN
IN
IN−
7
7
7
7
7
7
7