AD7938 Analog Devices, AD7938 Datasheet - Page 27

• Manufacturer Part Number: AD7938
• Description: 8-Channel, 1.5 MSPS, 12-Bit Parallel ADCs with a Sequencer
• Manufacturer: Analog Devices

Specifications of AD7938

• Resolution (bits): 12bit
• # Chan: 8
• Sample Rate: 1.5MSPS
• Interface: Byte,Par
• Analog Input Type: Diff-Uni,SE-Uni
• Ain Range: (2Vref) p-p,5V p-p,Uni (Vref),Uni (Vref) x 2,Uni 2.5V,Uni 5.0V
• Adc Architecture: SAR
• Pkg Type: CSP,QFP

Data Sheet
Writing Data to the AD7938/AD7939
With W/ B tied logic high, a single write operation transfers the
full data-word on DB0 to DB11 to the control register on the
AD7938/AD7939. The DB8/HBEN pin assumes its DB8
function. Data written to the AD7938/AD7939 should be
provided on the DB0 to DB11 inputs, with DB0 being the LSB
of the data-word. With W/ B tied logic low, the
AD7938/AD7939 requires two write operations to transfer a full
12-bit word. DB8/HBEN assumes its HBEN function. Data
written to the AD7938/AD7939 should be provided on the DB0
to DB7 inputs. HBEN determines whether the byte written is
high byte or low byte data. The low byte of the data-word
should be written first with DB0 being the LSB of the full data-
word. For the high byte write, HBEN should be high and the
data on the DB0 input should be data Bit 8 of the 12-bit word.
In both word and byte mode, a single write operation to the
shadow register is always sufficient since it is only eight bits
wide.
Figure 38. AD7938/AD7939 Parallel Interface—Write Cycle Timing for Word Mode Operation (W/ B = 1)
DB0 TO DB11
Figure 39. AD7938/AD7939 Parallel Interface—Write Cycle Timing for Byte Mode Operation (W/ B = 0)
HBEN/DB8
WR
CS
DB0 TO DB11
WR
CS
t
18
t
4
t
LOW BYTE
4
t
Rev. C | Page 27 of 36
6
t
7
t
5
t
19
t
6
DATA
t
t
7
8
Figure 38 shows the write cycle timing diagram of the
AD7938/AD7939 in word mode. When operating in word
mode, the HBEN input does not exist and only one write
operation is required to write the word of data to the device.
Data should be provided on DB0 to DB11. When operating in
byte mode, the two write cycles shown in Figure 39 are required
to write the full data-word to the AD7938/AD7939. In Figure 39,
the first write transfers the lower eight bits of the data-word
from DB0 to DB7, and the second write transfers the upper four
bits of the data-word. When writing to the AD7938/AD7939, the
top four bits in the high byte must be 0s.
The data is latched into the device on the rising edge of WR .
The data needs to be setup a time, t
and held for a time, t
WR signals are gated internally. CS and WR can be tied
together as the timing specifications for t
minimum (assuming CS and RD have not already been tied
together).
t
17
t
8
t
t
5
18
HIGH BYTE
8
, after the WR rising edge. The CS and
t
19
7
, before the WR rising edge
AD7938/AD7939
4
and t
5
are 0 ns