AD7938 Analog Devices, AD7938 Datasheet - Page 9

• Manufacturer Part Number: AD7938
• Description: 8-Channel, 1.5 MSPS, 12-Bit Parallel ADCs with a Sequencer
• Manufacturer: Analog Devices

Specifications of AD7938

• Resolution (bits): 12bit
• # Chan: 8
• Sample Rate: 1.5MSPS
• Interface: Byte,Par
• Analog Input Type: Diff-Uni,SE-Uni
• Ain Range: (2Vref) p-p,5V p-p,Uni (Vref),Uni (Vref) x 2,Uni 2.5V,Uni 5.0V
• Adc Architecture: SAR
• Pkg Type: CSP,QFP

Data Sheet
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Table 6. Pin Function Descriptions
Pin No.
1 to 8
9
10
11
12 to
14
15
16
17
18
19
20
NOTES
1. THE EXPOSED PAD IS LOCATED ON THE UNDERSIDE OF
DB0
DB1
DB2
DB3
DB4
DB5
DB6
DB7
THE PACKAGE. CONNECT THE EPAD TO THE GROUND
PLANE OF THE PCB USING MULTIPLE VIAS.
Mnemonic
DB0 to DB7
V
DGND
DB8/HBEN
DB9 to
DB11
BUSY
CLKIN
CONVST
WR
RD
CS
DRIVE
1
2
3
4
5
6
7
8
AD7938/AD7939
Figure 2. LFCSP Pin Configuration
(Not to Scale)
PIN 1
INDICATOR
TOP VIEW
Description
Data Bit 0 to Data Bit 7. Three-state parallel digital I/O pins that provide the conversion result and allow the control
and shadow registers to be programmed. These pins are controlled by CS, RD, and WR. The logic high/low voltage
levels for these pins are determined by the V
DB1) are always 0 and the LSB of the conversion result is available on DB2.
Logic Power Supply Input. The voltage supplied at this pin determines at what voltage the parallel interface of the
AD7938/AD7939 operates. This pin should be decoupled to DGND. The voltage at this pin can be different to that
at V
Digital Ground. This is the ground reference point for all digital circuitry on the AD7938/AD7939. This pin should
connect to the DGND plane of a system. The DGND and AGND voltages should ideally be at the same potential
and must not be more than 0.3 V apart, even on a transient basis.
Data Bit 8/High Byte Enable. When W/B is high, this pin acts as Data Bit 8, a three-state I/O pin that is controlled by
CS, RD, and WR. When W/B is low, this pin acts as the high byte enable pin. When HBEN is low, the low byte of data
being written to or read from the AD7938/AD7939 is on DB0 to DB7. When HBEN is high, the top four bits of the
data being written to or read from the AD7938/AD7939 are on DB0 to DB3. When reading from the device, DB4 to
DB6 of the high byte contains the ID of the channel to which the conversion result corresponds (see the channel
address bits in Table 10). When writing to the device, DB4 to DB7 of the high byte must be all 0s. Note that when
reading from the AD7939, the two LSBs of the low byte are 0s, and the remaining six bits are conversion data.
Data Bit 9 to Data Bit 11. Three-state parallel digital I/O pins that provide the conversion result and allow the
control and shadow registers to be programmed in word mode. These pins are controlled by CS, RD, and WR. The
logic high/low voltage levels for these pins are determined by the V
Busy Output. Logic output that indicates the status of the conversion. The BUSY output goes high following the
falling edge of CONVST and stays high for the duration of the conversion. Once the conversion is complete and the
result is available in the output register, the BUSY output goes low. The track-and-hold returns to track mode just
prior to the falling edge of BUSY on the 13
Master Clock Input. The clock source for the conversion process is applied to this pin. Conversion time for the
AD7938/AD7939 takes 13 clock cycles + t
conversion time and achievable throughput rate. The CLKIN signal may be a continuous or burst clock.
Conversion Start Input. A falling edge on CONVST is used to initiate a conversion. The track-and-hold goes from track
mode to hold mode on the falling edge of CONVST and the conversion process is initiated at this point. Following
power-down, when operating in autoshutdown or autostandby modes, a rising edge on CONVST is used to power up
the device.
Write Input. Active low logic input used in conjunction with CS to write data to the internal registers.
Read Input. Active low logic input used in conjunction with CS to access the conversion result. The conversion
result is placed on the data bus following the falling edge of RD read while CS is low.
Chip Select. Active low logic input used in conjunction with RD and WR to read conversion data or to write data to
the internal registers.
DD
but should never exceed V
24 V
23 V
22 V
21 AGND
20 CS
19 RD
18 WR
17 CONVST
IN
IN
REFIN
1
0
/V
REFOUT
DD
by more than 0.3 V.
Rev. C | Page 9 of 36
2
. The frequency of the master clock input therefore determines the
th
rising edge of CLKIN. See Figure 36.
DRIVE
input. When reading from the AD7939, the two LSBs (DB0 and
DB0
DB1
DB3
DB4
DB5
DB6
DB7
DB2
1
2
3
4
5
6
7
8
32 31 30 29 28 27 26 25
9
DRIVE
Figure 3. TQFP Pin Configuration
AD7938/AD7939
10 11 12 13 14 15 16
PIN 1
input.
(Not to Scale)
TOP VIEW
AD7938/AD7939
24
23
22
21
20
19
18
17
V
V
V
AGND
CS
RD
WR
CONVST
IN
IN
REFIN
1
0
/V
REFOUT