AD7938 Analog Devices, AD7938 Datasheet - Page 26

• Manufacturer Part Number: AD7938
• Description: 8-Channel, 1.5 MSPS, 12-Bit Parallel ADCs with a Sequencer
• Manufacturer: Analog Devices

Specifications of AD7938

• Resolution (bits): 12bit
• # Chan: 8
• Sample Rate: 1.5MSPS
• Interface: Byte,Par
• Analog Input Type: Diff-Uni,SE-Uni
• Ain Range: (2Vref) p-p,5V p-p,Uni (Vref),Uni (Vref) x 2,Uni 2.5V,Uni 5.0V
• Adc Architecture: SAR
• Pkg Type: CSP,QFP

AD7938/AD7939
Reading Data from the AD7938/AD7939
With the W/ B pin tied logic high, the AD7938/AD7939
interface operates in word mode. In this case, a single read
operation from the device accesses the conversion data-word
on Pins DB0/DB2 to Pin DB11. The DB8/HBEN pin assumes
its DB8 function. With the W/ B pin tied to logic low, the
AD7938/AD7939 interface operates in byte mode. In this case,
the DB8/HBEN pin assumes its HBEN function. Conversion
data from the AD7938/AD7939 must be accessed in two read
operations with eight bits of data provided on DB0 to DB7 for
each of the read operations. The HBEN pin determines whether
the read operation accesses the high byte or the low byte of the
12-bit or 10-bit word. For a low byte read, DB0 to DB7 provide
the eight LSBs of the 12-bit word. For 10-bit operation, the two
LSBs of the low byte are 0s, followed by six bits of conversion
data. For a high byte read, DB0 to DB3 provide the four MSBs
of the 12-bit or10-bit word. DB5 to DB7 of the high byte
provide the channel ID. Figure 36 shows the read cycle timing
diagram for a 12-bit or 10-bit transfer. When operating in word
mode, the HBEN input does not exist, and only the first read
operation is required to access data from the device. When
operating in byte mode, the two read cycles shown in Figure 37
are required to access the full data-word from the device.
Figure 37. AD7938/AD7939 Parallel Interface—Read Cycle Timing for Byte Mode Operation (W/ B = 0)
DB0 TO DB7
HBEN/DB8
RD
CS
t
t
13
15
t
10
LOW BYTE
t
12
Rev. C | Page 26 of 36
t
11
t
16
t
14
The CS and RD signals are gated internally and the level is
triggered active low. In either word mode or byte mode, CS and
RD can be tied together because the timing specifications for t
and t
driven by the AD7938/AD7939.
The data is placed onto the data bus a time t
RD go low. The RD rising edge can be used to latch data out of
the device. After a time, t
Alternatively, CS and RD can be tied permanently low and the
conversion data is valid and placed onto the data bus a time, t
before the falling edge of BUSY.
Note that if RD is pulsed during the conversion time, this
causes a degradation in linearity performance of approximately
0.25 LSB. Reading during conversion by way of tying CS and
RD low does not cause any degradation.
t
17
11
are 0 ns minimum. This means the bus is constantly
t
15
HIGH BYTE
14
, the data lines become three-stated.
t
16
13
after both CS and
Data Sheet
9
,
10