AD7938 Analog Devices, AD7938 Datasheet - Page 7

no-image

AD7938

Manufacturer Part Number
AD7938
Description
8-Channel, 1.5 MSPS, 12-Bit Parallel ADCs with a Sequencer
Manufacturer
Analog Devices
Datasheet

Specifications of AD7938

Resolution (bits)
12bit
# Chan
8
Sample Rate
1.5MSPS
Interface
Byte,Par
Analog Input Type
Diff-Uni,SE-Uni
Ain Range
(2Vref) p-p,5V p-p,Uni (Vref),Uni (Vref) x 2,Uni 2.5V,Uni 5.0V
Adc Architecture
SAR
Pkg Type
CSP,QFP

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
AD7938BCP
Manufacturer:
AGILENT
Quantity:
2 852
Part Number:
AD7938BSU
Manufacturer:
ADI
Quantity:
329
Part Number:
AD7938BSU-6
Manufacturer:
ADI
Quantity:
230
Part Number:
AD7938BSUZ
Manufacturer:
ADI
Quantity:
455
Part Number:
AD7938BSUZ
Manufacturer:
Analog Devices Inc
Quantity:
10 000
Part Number:
AD7938BSUZ
Manufacturer:
ADI/亚德诺
Quantity:
20 000
Part Number:
AD7938BSUZ-6
Manufacturer:
ADI
Quantity:
230
Part Number:
AD7938BSUZ-6
Manufacturer:
Analog Devices Inc
Quantity:
10 000
Part Number:
AD7938BSUZ-6
Manufacturer:
ADI/亚德诺
Quantity:
20 000
Part Number:
AD7938BSUZ-6REEL7
Manufacturer:
Analog Devices Inc
Quantity:
10 000
Part Number:
AD7938BSUZ-REEL7
Manufacturer:
Analog Devices Inc
Quantity:
10 000
Data Sheet
TIMING SPECIFICATIONS
V
T
Table 4.
Parameter
f
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
1
2
3
4
CLKIN
QUIET
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
1.6 V. All timing specifications given above are with a 25 pF load capacitance (see Figure 36, Figure 37, Figure 38, and Figure 39).
Sample tested during initial release to ensure compliance. All input signals are specified with t
Minimum CLKIN for specified performance, with slower SCLK frequencies performance specifications apply typically.
The time required for the output to cross 0.4 V or 2.4 V.
t
discharging the 25 pF capacitor. This means that the time, t
bus loading.
MAX
14
DD
3
4
is derived from the measured time taken by the data outputs to change 0.5 V. The measured number is then extrapolated back to remove the effects of charging or
= V
2
, unless otherwise noted.
DRIVE
1
= 2.7 V to 5.25 V, internal/external V
AD7938
700
25.5
30
10
15
50
0
0
10
10
10
10
0
0
30
30
3
50
0
0
10
0
10
40
15.7
7.8
Limit at T
MIN
AD7939
700
25.5
30
10
15
50
0
0
10
10
10
10
0
0
30
30
3
50
0
0
10
0
10
40
15.7
7.8
, T
MAX
Unit
kHz min
MHz max
ns min
ns min
ns min
ns max
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns max
ns min
ns max
ns min
ns min
ns min
ns min
ns min
ns max
ns min
ns min
Description
CLKIN frequency.
Minimum time between end of read and start of next conversion; in other words, time
from when the data bus goes into three-state until the next falling edge of CONVST.
CONVST pulse width.
CONVST falling edge to CLKIN falling edge setup time.
CLKIN falling edge to BUSY rising edge.
CS to WR setup time.
CS to WR hold time.
WR pulse width.
Data setup time before WR.
Data hold after WR.
New data valid before falling edge of BUSY.
CS to RD setup time.
CS to RD hold time.
RD pulse width.
Data access time after RD.
Bus relinquish time after RD.
Bus relinquish time after RD.
HBEN to RD setup time.
HBEN to RD hold time.
Minimum time between reads/writes.
HBEN to WR setup time.
HBEN to WR hold time.
CLKIN falling edge to BUSY falling edge.
CLKIN low pulse width.
CLKIN high pulse width.
14
REF
, quoted in the timing characteristics is the true bus relinquish time of the part and is independent of the
= 2.5 V, unless otherwise noted; f
Rev. C | Page 7 of 36
RISE
= t
FALL
= 5 ns (10% to 90% of V
CLKIN
= 25.5 MHz, f
SAMPLE
DD
) and timed from a voltage level of
= 1.5 MSPS; T
AD7938/AD7939
A
= T
MIN
to

Related parts for AD7938