AD7478 Analog Devices, AD7478 Datasheet - Page 13

• Manufacturer Part Number: AD7478
• Description: 8-Bit, 1 MSPS, Low Power Successive Approximation ADC Which Operates From A Single 2.35 V to 5.25 V Power Supply
• Manufacturer: Analog Devices

Specifications of AD7478

• Resolution (bits): 8bit
• # Chan: 1
• Sample Rate: 1MSPS
• Interface: Ser,SPI
• Analog Input Type: SE-Uni
• Ain Range: Uni Vdd
• Adc Architecture: SAR
• Pkg Type: SOT

THEORY OF OPERATION
CIRCUIT INFORMATION
The AD7476/AD7477/AD7478 are, respectively, 12-bit, 10-bit,
and 8-bit, fast, micropower, single-supply ADCs. The parts can
be operated from a 2.35 V to 5.25 V supply. When operated
from either a 5 V supply or a 3 V supply, the AD7476/AD7477/
AD7478 are capable of throughput rates of 1 MSPS when
provided with a 20 MHz clock.
Each AD7476/AD7477/AD7478 provides an on-chip, track-
and-hold ADC and a serial interface housed in a tiny 6-lead
SOT-23 package, which offers considerable space-saving
advantages. The serial clock input accesses data from the part
and provides the clock source for the successive-approximation
ADC. The analog input range is 0 V to V
reference is not required for the ADC, nor is there a reference
on-chip. The reference for the AD7476/AD7477/AD7478 is
derived from the power supply and thus provides the widest
dynamic input range.
The AD7476/AD7477/AD7478 also feature a power-down
option to save power between conversions. The power-down
feature is implemented across the standard serial interface as
described in the Modes of Operation section.
CONVERTER OPERATION
The AD7476/AD7477/AD7478 are successive-approximation
analog-to-digital converters based around a charge redistribu-
tion DAC. Figure 1 and Figure 11 show simplified schematics
of the ADC. Figure 10 shows the ADC during its acquisition
phase. SW2 is closed and SW1 is in Position A, the comparator
is held in a balanced condition, and the sampling capacitor
acquires the signal on V
When the ADC starts a conversion (see Figure 11), SW2 opens
and SW1 moves to Position B, causing the comparator to
become unbalanced. The control logic and the charge redistri-
bution DAC are used to add and subtract fixed amounts of
charge from the sampling capacitor to bring the comparator
back into a balanced condition. When the comparator is rebal-
anced, the conversion is complete. The control logic generates
the ADC output code. Figure 12 and Figure 13 show the ADC
transfer function.
V
IN
SW1
AGND
A
B
ACQUISITION
CAPACITOR
SAMPLING
Figure 10. ADC Acquisition Phase
PHASE
V
DD
/2
IN
.
SW2
COMPARATOR
DD
. An external
REDISTRIBUTION
CONTROL
CHARGE
LOGIC
DAC
Rev. F | Page 13 of 24
ADC TRANSFER FUNCTION
The output coding of the AD7476/AD7477/AD7478 is straight
binary. For the AD7476/AD7477, designed code transitions
occur midway between successive integer LSB values, such as ½
LSB, 1½ LSB, and so on. The LSB size for the AD7476 is
V
ideal transfer characteristic for the AD7476/AD7477 is shown
in Figure 12.
For the AD7478, designed code transitions occur midway
between successive integer LSB values, such as 1 LSB, 2 LSB,
and so on. The LSB size for the AD7478 is V
transfer characteristic for the AD7478 is shown in Figure 13.
DD
/4096, and the LSB size for the AD7477 is V
V
111 ... 111
111 ... 110
111 ... 000
011 ... 111
000 ... 010
000 ... 001
000 ... 000
111 ... 111
111 ... 110
111 ... 000
011 ... 111
000 ... 010
000 ... 001
000 ... 000
IN
Figure 12. Transfer Characteristic for the AD7476/AD7477
SW1
AGND
Figure 13. Transfer Characteristic for AD7478
A
B
0V
0V
CONVERSION
CAPACITOR
SAMPLING
0.5LSB
1LSB
Figure 11. ADC Conversion Phase
PHASE
V
DD
/2
AD7476/AD7477/AD7478
SW2
ANALOG INPUT
ANALOG INPUT
COMPARATOR
1LSB = V
1LSB = V
1LSB = V
+V
+V
DD
DD
DD
DD
REDISTRIBUTION
DD
DD
/4096 (AD7476)
/1024 (AD7477)
/256 (AD7478)
/256. The ideal
DD
– 1LSB
CONTROL
– 1.5LSB
CHARGE
LOGIC
/1024. The
DAC