AD7478 Analog Devices, AD7478 Datasheet - Page 15

• Manufacturer Part Number: AD7478
• Description: 8-Bit, 1 MSPS, Low Power Successive Approximation ADC Which Operates From A Single 2.35 V to 5.25 V Power Supply
• Manufacturer: Analog Devices

Specifications of AD7478

• Resolution (bits): 8bit
• # Chan: 1
• Sample Rate: 1MSPS
• Interface: Ser,SPI
• Analog Input Type: SE-Uni
• Ain Range: Uni Vdd
• Adc Architecture: SAR
• Pkg Type: SOT

Figure 16. THD vs. Source Impedance for Various Analog Input Frequencies
–100
–50
–55
–60
–65
–70
–75
–80
–85
–90
–72
–74
–76
–78
–80
–82
–84
–10
–20
–30
–40
–50
–60
–70
–80
–90
Figure 17. THD vs. Analog Input Frequency, f
Figure 18. THD vs. Analog Input Frequency, f
0
10k
10k
1
10
SOURCE IMPEDANCE (Ω)
INPUT FREQUENCY (Hz)
INPUT FREQUENCY (Hz)
f
IN
= 300kHz
100k
100k
100
V
DD
f
IN
= 5.25V
= 10kHz
V
DD
V
= 2.35V
DD
V
V
s
s
1k
DD
DD
= 993 kSPS
= 2.7V
V
V
= 605 kSPS
f
V
DD
DD
V
f
IN
f
V
= 3.6V
= 3.6V
S
IN
DD
DD
DD
= 200kHz
= 605kSPS
V
= 4.75V
= 5.25V
= 100kHz
DD
= 4.75V
= 2.7V
= 2.35V
= 2.7V
10k
1M
1M
Rev. F | Page 15 of 24
Digital Input
The digital input applied to the AD7476/AD7477/AD7478 is
not limited by the maximum ratings that limit the analog input.
Instead, the digital input applied can go to 7 V and is not
restricted by the V
example, if the AD7476/AD7477/AD7478 are operated with a
V
However, note that the data output on SDATA still has 3 V logic
levels when V
being restricted by the V
sequencing issues are avoided. If CS or SCLK is applied before
V
when a signal greater than 0.3 V is applied prior to V
MODES OF OPERATION
Select the mode of operation of the AD7476/AD7477/AD7478
by controlling the (logic) state of the CS signal during a
conversion. The two possible modes of operation are normal
mode and power-down mode. The point at which CS is pulled
high after the conversion has been initiated determines whether
or not the AD7476/AD7477/AD7478 enters power-down mode.
Similarly, if already in power-down, CS can control whether the
device returns to normal operation or remains in power-down.
These modes of operation are designed to provide flexible
power management options. These options can be chosen to
optimize the power dissipation/throughput rate ratio for
different application requirements.
Normal Mode
This mode is intended for fastest throughput rate performance.
Users do not have to worry about power-up times with the
AD7476/AD7477/AD7478 remaining fully powered at all times.
Figure 19 shows the general diagram of the AD7476/AD7477/
AD7478 in normal mode.
The conversion is initiated on the falling edge of CS as de-
scribed in the
remains fully powered up at all times,
at least 10 SCLK falling edges have elapsed after the falling edge
of CS . If CS is brought high any time after the tenth SCLK
falling edge, but before the sixteenth SCLK falling edge, the part
remains powered up, but the conversion terminates and SDATA
goes back into three-state. Sixteen serial clock cycles are
required to complete the conversion and access the complete
conversion result. CS may idle high until the next conversion or
may idle low until CS returns high sometime prior to the next
conversion (effectively idling CS low).
Once a data transfer is complete, (SDATA has returned to three-
state), another conversion can be initiated after the quiet time,
t
QUIET
DD
DD
, there is no risk of latch-up as there is on the analog input
of 3 V, then 5 V logic levels can be used on the digital input.
, has elapsed by again bringing CS low.
DD
Serial Interface
= 3 V. Another advantage of SCLK and CS not
DD
+ 0.3 V limit as on the analog input. For
DD
AD7476/AD7477/AD7478
+ 0.3 V limit is that power supply
section. To ensure the part
CS must remain low until
DD
.