AD7478 Analog Devices, AD7478 Datasheet - Page 8

• Manufacturer Part Number: AD7478
• Description: 8-Bit, 1 MSPS, Low Power Successive Approximation ADC Which Operates From A Single 2.35 V to 5.25 V Power Supply
• Manufacturer: Analog Devices

Specifications of AD7478

• Resolution (bits): 8bit
• # Chan: 1
• Sample Rate: 1MSPS
• Interface: Ser,SPI
• Analog Input Type: SE-Uni
• Ain Range: Uni Vdd
• Adc Architecture: SAR
• Pkg Type: SOT

AD7476/AD7477/AD7478
Parameter
1
2
3
4
5
TIMING SPECIFICATIONS
V
Table 4.
Parameter
f
t
t
t
t
t
t
t
t
t
t
t
1
2
3
4
5
6
7
SCLK
CONVERT
QUIET
1
2
3
4
5
6
7
8
POWER-UP
Temperature range for A version is −40°C to +85°C; temperature range for S version is −55°C to +125°C.
Operational from V
See the Terminology section.
Guaranteed by characterization.
See the Power vs. Throughput Rate section.
3 V specifications apply from V
V
Guaranteed by characterization. All input signals are specified with tr = tf = 5 ns (10% to 90% of V
Version A timing specifications apply to the AD7477 and AD7478 S version; B version timing specifications apply to the AD7476 S version.
Mark/space ratio for the SCLK input is 40/60 to 60/40.
Measured with the load circuit of Figure 2 and defined as the time required for the output to cross 0.8 V or 2.0 V.
t
remove the effects of charging or discharging the 50 pF capacitor. This means that the time, t
loading.
See Power-Up Time section.
5
DD
5
6
8
DD
is derived from the measured time taken by the data output to change 0.5 V when loaded with the circuit in Figure 2. The measured number is then extrapolated to
Power Dissipation
4
= 4.75 V to 5.25 V.
= 2.35 V to 5.25 V, T
Normal Mode (Operational)
Full Power-Down
7
2,3
3 V
10
20
12
16 × t
50
10
10
20
40
70
0.4 ×
t
0.4 ×
t
10
10
25
1
DD
SCLK
SCLK
Limit at T
= 2.0 V, with input high voltage, V
5
SCLK
A
DD
= T
MIN
5 V
10
20
12
16 × t
50
10
10
20
20
20
0.4 ×
t
0.4 ×
t
10
10
25
1
= 2.7 V to 3.6 V for A version; 3 V specifications apply from V
SCLK
SCLK
, T
MIN
MAX
to T
SCLK
1
MAX
Unit
kHz min
MHz
max
MHz
max
ns min
ns min
ns min
ns max
ns max
ns max
ns min
ns min
ns min
ns min
ns max
μs typ
, unless otherwise noted.
Figure 2. Load Circuit for Digital Output Timing Specifications
INH
= 1.8 V minimum.
A Version
17.5
4.8
5
TO OUTPUT
Description
A version
B version
Minimum quiet time required between bus relinquish and start of next conversion
Minimum CS pulsewidth
CS to SCLK setup time
Delay from CS until SDATA three-state disabled
Data access time after SCLK falling edge, A version
Data access time after SCLK falling edge, B version
SCLK low pulsewidth
SCLK high pulsewidth
SCLK to data valid hold time
SCLK falling edge to SDATA high impedance
SCLK falling edge to SDATA high impedance
Power-up time from full power-down
PIN
1,2
Rev. F | Page 8 of 24
50pF
C
L
S Version
17.5
4.8
5
200µA
200µA
1,2
I
I
OL
OH
DD
8
, is the true bus relinquish time of the part and is independent of the bus
= 2.35 V to 3.6 V for B version; 5 V specifications apply from
DD
Unit
mW max
mW max
μW max
) and timed from a voltage level of 1.6 V.
1.6V
Test Conditions/Comments
V
V
V
DD
DD
DD
= 5 V, f
= 3 V, f
= 5 V, SCLK off
SAMPLE
SAMPLE
= 1 MSPS
= 1 MSPS