AD7478 Analog Devices, AD7478 Datasheet - Page 19

• Manufacturer Part Number: AD7478
• Description: 8-Bit, 1 MSPS, Low Power Successive Approximation ADC Which Operates From A Single 2.35 V to 5.25 V Power Supply
• Manufacturer: Analog Devices

Specifications of AD7478

• Resolution (bits): 8bit
• # Chan: 1
• Sample Rate: 1MSPS
• Interface: Ser,SPI
• Analog Input Type: SE-Uni
• Ain Range: Uni Vdd
• Adc Architecture: SAR
• Pkg Type: SOT

MICROPROCESSOR INTERFACING
The serial interface on the AD7476/AD7477/AD7478 allows the
part to be directly connected to a range of many different
microprocessors. This section explains how to interface the
AD7476/AD7477/AD7478 with some of the more common
microcontroller and DSP serial interface protocols.
AD7476/AD7477/AD7478 to TMS320C5x/C54x Interface
The serial interface on the TMS320C5x uses a continuous serial
clock and frame synchronization signals to synchronize the data
transfer operations with peripheral devices such as the AD7476/
AD7477/AD7478. The CS input allows easy interfacing between
the TMS320C5x/C54x and the AD7476/AD7477/AD7478
without any glue logic required. In addition, the serial port of
the TMS320C5x/C54x is set up to operate in burst mode with
internal CLKX (Tx serial clock) and FSX (Tx frame sync).
The serial port control register (SPC) must have the following
setup: FO = 0, FSM = 1, MCM = 1, and TXM = 1. The format
bit, FO, can be set to 1 to set the word length to eight bits, in
order to implement the power-down mode on the AD7476/
AD7477/AD7478. The connection diagram is shown in
Figure 26. Note that for signal processing applications, it is
imperative that the frame synchronization signal from the
TMS320C5x/C54x provides equidistant sampling.
AD7476/AD7477/AD7478 to ADSP-21xx Interface
The ADSP-21xx family of DSPs are interfaced directly to the
AD7476/AD7477/AD7478 without any glue logic required. The
SPORT control register is set up as follows:
To implement the power-down mode, SLEN is set to 0111 to
issue an 8-bit SCLK burst. The connection diagram is shown in
Figure 27. The ADSP-21xx has the TFS and RFS of the SPORT
tied together, with TFS set as an output and RFS set as an input.
The DSP operates in alternate framing mode and the SPORT
control register is set up as described.
TFSW = RFSW = 1, Alternate Framing
INVRFS = INVTFS = 1, Active Low Frame Signal
DTYPE = 00, Right Justify Data
SLEN = 1111, 16-Bit Data-Words
ISCLK = 1, Internal Serial Clock
TFSR = RFSR = 1, Frame Every Word
IRFS = 0
ITFS = 1
Figure 26. Interfacing to the TMS320C5x/C54x
AD7478
AD7476/
AD7477/
1
ADDITIONAL PINS OMITTED FOR CLARITY
SDATA
SCLK
CS
1
TMS320C54x
TMS320C5x/
CLKX
CLKR
DR
FSX
FSR
1
Rev. F | Page 19 of 24
The frame synchronization signal generated on the TFS is tied
to CS and, as with all signal processing applications, equidistant
sampling is necessary. However, in this example, the timer
interrupt controls the sampling rate of the ADC and, under
certain conditions, equidistant sampling may not be achieved.
The timer registers, for example, are loaded with a value that
provides an interrupt at the required sample interval. When an
interrupt is received, a value is transmitted with TFS/DT (ADC
control word). The TFS controls the RFS and, therefore, the
reading of data. The frequency of the serial clock is set in the
SCLKDIV register. When the instruction to transmit with TFS
is given, such as, TX0 = AX0, the state of the SCLK is checked.
The DSP waits until the SCLK has gone high, low, and high
before transmission starts. If the timer and SCLK values are
chosen such that the instruction to transmit occurs on or near
the rising edge of SCLK, the data could be transmitted, or it
could wait until the next clock edge.
For example, the ADSP-2111 has a master clock frequency of
16 MHz. If the SCLKDIV register is loaded with the value 3, a
SCLK of 2 MHz is obtained, and eight master clock periods
elapse for every one SCLK period. If the timer registers are
loaded with the value 803, 100.5 SCLKs occur between
interrupts and, subsequently, between transmit instructions.
This situation results in nonequidistant sampling as the
transmit instruction is occurring on an SCLK edge. If the
number of SCLKs between interrupts is a whole integer figure
of N, equidistant sampling is implemented by the DSP.
AD7476/AD7477/AD7478 to DSP56xxx Interface
The connection diagram in Figure 28 shows how the AD7476/
AD7477/AD7478 can be connected to the synchronous serial
interface (SSI) of the DSP56xxx family of DSPs from Motorola.
The SSI is operated in synchronous mode (SYN bit in CRB =1)
with internally generated word frame sync for both Tx and Rx
(Bits FSL1 = 0 and FSL0 = 0 in CRB). Set the word length to 16
by setting bits WL1 = 1 and WL0 = 0 in CRA.
To implement the power-down mode on the AD7476/AD7477/
AD7478, the word length can be changed to eight bits by setting
bits WL1 = 0 and WL0 = 0 in CRA. Note that for signal process-
ing applications, it is imperative that the frame synchronization
signal from the DSP56xxx provides equidistant sampling.
AD7476/
AD7477/
AD7478
1
ADDITIONAL PINS OMITTED FOR CLARITY
Figure 27. Interfacing to the ADSP-21xx
SDATA
SCLK
CS
1
AD7476/AD7477/AD7478
ADSP-21xx
SCLK
DR
RFS
TFS
1