AD8067 Analog Devices, AD8067 Datasheet - Page 16

• Manufacturer Part Number: AD8067
• Manufacturer: Analog Devices

Specifications of AD8067

• Vcc-vee: 5V to 24V
• Isy Per Amplifier: 7mA
• Packages: SOT
• -3db Bandwidth: 54MHz
• Slew Rate: 640V/µs
• Vos: 200µV
• Ib: 0.6pA
• # Opamps Per Pkg: 1
• Input Noise (nv/rthz): 6.6nV/rtHz

AD8067
INPUT PROTECTION
The inputs of the AD8067 are protected with back-to-back
diodes between the input terminals as well as ESD diodes to
either power supply. The result is an input stage with picoamp
level input currents that can withstand 2 kV ESD events
(human body model) with no degradation.
Excessive power dissipation through the protection devices
destroys or degrades the performance of the amplifier.
Differential voltages greater than 0.7 V result in an input
current of approximately (| V
where R
voltages beyond the positive supply, the input current is about
(V
supply, the input current is about (V
of these conditions, R
input current to 50 mA or less.
R
FOR LARGE |V+ – V– |
CAPACITIVE LOAD DRIVE
Capacitive load introduces a pole in the amplifier loop response
due to the finite output impedance of the amplifier. This can
cause excessive peaking and ringing in the response. The
AD8067 with a gain of +10 handles up to a 30 pF capacitive
load without an excessive amount of peaking (see Figure 8). If
greater capacitive load drive is required, consider inserting a
small resistor in series with the load (24.9 Ω is a good value to
start with). Capacitive load drive capability also increases as the
gain of the amplifier increases.
I
> ( |V+ – V– | –0.7V)/50mA
I
– V
CC
I
–
and R
– 0.7 V)/R
V
I
+
G
R
are the resistors (see Figure 46). For input
I
Figure 46. Current Limiting Resistor
R
I
G
. For input voltages beyond the negative
I
should be sized to limit the resulting
AD8067
R
F
+
– V
−
| − 0.7 V)/(R
I
– V
EE
V
+
–
OUT
+ 0.7 V)/R
R
R
FOR V
SUPPLY VOLTAGES
I
I
> (V
> (V
I
I
I
I
BEYOND
– V
– V
+ R
EE
CC
G
I
+ 0.7V)/50mA
)),
– 0.7V)/50mA
. For any
Rev. A | Page 16 of 24
LAYOUT, GROUNDING, AND BYPASSING
CONSIDERATIONS
Layout
In extremely low input bias current amplifier applications, stray
leakage current paths must be kept to a minimum. Any voltage
differential between the amplifier inputs and nearby traces sets
up a leakage path through the PCB. Consider a 1 V signal and
100 GΩ to ground present at the input of the amplifier. The
resultant leakage current is 10 pA; this is 10× the input bias
current of the amplifier. Poor PCB layout, contamination, and
the board material can create large leakage currents. Common
contaminants on boards are skin oils, moisture, solder flux, and
cleaning agents. Therefore, it is imperative that the board be
thoroughly cleaned and the board surface be free of contaminants
to fully take advantage of the AD8067’s low input bias currents.
To significantly reduce leakage paths, a guard-ring/shield
around the inputs should be used. The guard-ring circles the
input pins and is driven to the same potential as the input
signal, thereby reducing the potential difference between pins.
For the guard ring to be completely effective, it must be driven
by a relatively low impedance source and should completely
surround the input leads on all sides, above, and below, using a
multilayer board (see Figure 47). The SOT-23-5 package
presents a challenge in keeping the leakage paths to a minimum.
The pin spacing is very tight, so extra care must be used when
constructing the guard ring (see Figure 48 for recommended
guard-ring construction).
GUARD RING
V
+IN
–V
OUT
INVERTING
AD8067
Figure 48. Guard-Ring Layout SOT-23-5
Figure 47. Guard-Ring Configurations
INVERTING
–IN
+V
V
GUARD RING
+IN
–V
OUT
NONINVERTING
NONINVERTING
AD8067
–IN
+V