ADP1043A Analog Devices, ADP1043A Datasheet - Page 69

• Manufacturer Part Number: ADP1043A
• Description: Digital Controller for Isolated Power Supply Applications
• Manufacturer: Analog Devices

Table 120. Register 0x49—OUTC Rising Edge Dead Time in Resonant Mode
Bits
[7:0]
Table 121. Register 0x4A—Burst Mode Operation in Resonant Mode
Bits
[7:6]
[5:0]
Table 122. Register 0x4B—OUTC Falling Edge Dead Time in Resonant Mode
Bits
[7:0]
Table 123. Register 0x4D—OUTD Rising Edge Dead Time in Resonant Mode
Bits
[7:0]
Name
Δt
time of OUTC)
Name
Δt
time of OUTC)
Name
Δt
time of OUTD)
Name
Burst mode enable
Burst mode offset
5
6
7
(rising edge dead
(falling edge dead
(rising edge dead
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
These bits are used to enable or disable burst mode operation.
Description
This register sets Δt
of the switching cycle, t
from 0x00 to 0x7F, the rising edge of OUTC is trailing t
the rising edge of OUTC is leading t
Bit 7
0
0
…
0
1
…
1
Description
Bit 7
0
0
1
1
These bits, along with the highest switching frequency limit, determine the threshold value for
enabling burst mode operation. For information about how to set this value, see the Light Load
Operation (Burst Mode) section.
Description
This register sets Δt
switching cycle, t
Bit 7
0
0
…
1
Description
This register sets Δt
point of the switching cycle, t
value is from 0x00 to 0x7F, the rising edge of OUTD is trailing t
0xFF, the rising edge of OUTD is leading t
Bit 7
0
0
…
0
1
…
1
Bit 6
0
0
…
1
0
…
1
Bit 6
0
0
…
1
Bit 6
0
0
…
1
0
…
1
Bit 6
0
1
0
1
Rev. 0 | Page 69 of 72
C
. Each LSB corresponds to 5 ns of resolution.
5
6
7
Bit 5
0
0
…
1
0
…
1
Bit 5
0
0
…
1
Bit 5
0
0
…
1
0
…
1
, which is the difference between the rising edge of OUTC and the midpoint
, which is the leading time of the falling edge of OUTC from the end of the
, which is the difference between the rising edge of OUTD and the mid-
B
. Each LSB corresponds to 5 ns of resolution. When the register value is
Bit 4
0
0
…
1
0
…
1
Bit 4
0
0
…
1
B
Bit 4
0
0
…
1
0
…
1
Burst Mode
Disabled
Enabled for normal operation, but disabled during soft start
Disabled
Enabled for normal operation and during soft start
. Each LSB corresponds to 5 ns of resolution. When the register
B
.
Bit 3
0
0
…
1
0
…
1
Bit 3
0
0
…
1
Bit 3
0
0
…
1
0
…
1
B
.
Bit 2
0
0
…
1
0
…
1
Bit 2
0
0
…
1
Bit 2
0
0
…
1
0
…
1
B
. When the value is from 0x80 to 0xFF,
Bit 1
0
0
…
1
0
…
1
Bit 1
0
0
…
1
Bit 1
0
0
…
1
0
…
1
B
. When the value is from 0x80 to
Bit 0
Bit 0
Bit 0
0
1
…
1
0
…
1
0
1
…
1
0
1
…
1
0
…
1
Δt
0 ns
5 ns trailing
…
635 ns trailing
640 ns leading
…
5 ns leading
Δt
0
5
…
1275
Δt
0 ns
5 ns trailing
…
635 ns trailing
640 ns leading
…
5 ns leading
ADP1043A
5
6
7
(ns)