LPC1343FHN33 NXP Semiconductors, LPC1343FHN33 Datasheet - Page 35

• Manufacturer Part Number: LPC1343FHN33
• Description: The LPC1343FHN33 is a ARM Cortex-M3 based microcontroller for embedded applications featuring a high level of integration and low power consumption
• Manufacturer: NXP Semiconductors

NXP Semiconductors
[7]
[8]
[9]
[10] WAKEUP pin pulled HIGH externally. An external pull-up resistor is required on the RESET pin for the Deep power-down mode.
[11] Low-current mode PWR_LOW_CURRENT selected when running the set_power routine in the power profiles.
[12] Including voltage on outputs in 3-state mode.
[13] V
[14] 3-state outputs go into 3-state mode in Deep power-down mode.
[15] Allowed as long as the current limit does not exceed the maximum current allowed by the device.
[16] To V
[17] 3.0 V  V
[18] Includes external resistors of 33   1 % on USB_DP and USB_DM.
Table 8.
T
[1]
[2]
[3]
[4]
[5]
[6]
[7]
[8]
LPC1311_13_42_43
Product data sheet
Symbol
V
C
E
E
E
E
E
R
R
amb
IA
D
L(adj)
O
G
T
ia
vsi
i
For LPC1342/43: USB_DP and USB_DM pulled LOW externally.
IRC disabled; system oscillator enabled; system PLL enabled.
All oscillators and analog blocks turned off in the PDSLEEPCFG register; PDSLEEPCFG = 0x0000 0FFF.
The ADC is monotonic, there are no missing codes.
The differential linearity error (E
The integral non-linearity (E
appropriate adjustment of gain and offset errors. See
The offset error (E
ideal curve. See
The gain error (E
error, and the straight line which fits the ideal transfer curve. See
The absolute error (E
ADC and the ideal transfer curve. See
T
Input resistance R
= 40 C to +85 C unless otherwise specified; ADC frequency 4.5 MHz, V
amb
DD
SS
supply voltage must be present.
= 25 C; maximum sampling frequency f
.
ADC static characteristics
DD
Parameter
analog input voltage
analog input capacitance
differential linearity error
integral non-linearity
offset error
gain error
absolute error
voltage source interface
resistance
input resistance
 3.6 V.
Figure
G
i
O
) is the relative difference in percent between the straight line fitting the actual transfer curve after removing offset
depends on the sampling frequency f
) is the absolute difference between the straight line which fits the actual curve and the straight line which fits the
T
) is the maximum difference between the center of the steps of the actual transfer curve of the non-calibrated
8.
L(adj)
D
) is the peak difference between the center of the steps of the actual and the ideal transfer curve after
) is the difference between the actual step width and the ideal step width. See
Figure
All information provided in this document is subject to legal disclaimers.
Conditions
s
8.
= 400 kSamples/s and analog input capacitance C
Rev. 4 — 20 June 2011
Figure
s
: R
i
8.
= 1 / (f
Figure
s
 C
8.
ia
).
[1][2]
[7][8]
[3]
[4]
[5]
[6]
Min
0
-
-
-
-
-
-
-
-
32-bit ARM Cortex-M3 microcontroller
DD
LPC1311/13/42/43
= 2.5 V to 3.6 V.
Typ
-
-
-
-
-
-
-
-
-
ia
= 1 pF.
Max
V
1
1
1.5
3.5
0.6
4
40
2.5
Figure
© NXP B.V. 2011. All rights reserved.
DD
8.
Unit
V
pF
LSB
LSB
LSB
%
LSB
k
M
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